초록 ▼

A semiconductor integrated circuit device using precharge circuits free from the influence of a phase difference skew is provided. Each of the precharge circuits is controlled by a clock signal such that an arbitrary node in the circuit is precharged during a low level period or a high level period

A semiconductor integrated circuit device using precharge circuits free from the influence of a phase difference skew is provided. Each of the precharge circuits is controlled by a clock signal such that an arbitrary node in the circuit is precharged during a low level period or a high level period of the clock signal and the precharge circuit is operative during a high level period or a low level period of the clock signal. A first precharge circuit and a second precharge circuit having the same operational functions are arranged in parallel, and controlled by their respective clock signals to perform complementary operations, wherein the second precharge circuit is in an active period when the first precharge circuit is in a precharge period, and the second precharge circuit is in a precharge period when the first precharge circuit is in an active period.

대표청구항 ▼

[ What is claimed is:] [1.] A computer system having at least one processor and at least one memory, wherein said processor accesses said memory, said processor comprising:first latch means controlled by a first clock signal having a predetermined period for latching an input signal;first precharge

[ What is claimed is:] [1.] A computer system having at least one processor and at least one memory, wherein said processor accesses said memory, said processor comprising:first latch means controlled by a first clock signal having a predetermined period for latching an input signal;first precharge means controlled by a second clock signal having a period twice the period of said first clock signal, said first precharge means being precharged during one half of the period of said second clock signal and operative based on the input signal latched by said first latch means during the remaining half period of said second clock signal;second precharge means controlled by a third clock signal generated by inverting said second clock signal and arranged in parallel with said first precharge means, said second precharge means being operative based on a signal latched by said first latch means during one half of the period of said third clock signal and precharged during the remaining half period of said second clock signal;selector means for alternately selecting output signals of said first and second precharge means; andsecond latch means controlled by said first clock signal for latching an output signal of said selector means.