초록 ▼

The present invention defines a method for emulating an iterated process represented by a series of related tasks and a control mechanism that monitors and enables the iterative execution of those tasks until data associated with the process converges to predetermined goals or objectives. The invent

The present invention defines a method for emulating an iterated process represented by a series of related tasks and a control mechanism that monitors and enables the iterative execution of those tasks until data associated with the process converges to predetermined goals or objectives. The invention defines a method in which fuzzy neural networks and discreet algorithms are applied to perform the process tasks and in which configurable, reloadable finite state machines are applied to control the execution of those tasks. In particular, the present invention provides a method for emulating the process of designing integrated circuit (IC) applications and printed circuit board (PCB) applications for the purpose of simulating, emulating, analyzing, optimizing and predicting the behavioral and physical characteristics of the application at the earliest possible stage of the process. The invention applies fuzzy neural networks and configurable, reloadable finite state machines to emulate the IC or PCB design process, enabling the invention to emulate the the computer aided design (CAD) tools used to perform the design process tasks as well as the individuals using those tools. By emulating the combination of man and machine performances, the invention can more accurately predict the results of a given task than tools that consider only the machine element. The invention also provides a means to adapt the performance and behavior of any element of the invention using historical data compiled from previous design or manufacturing experiences, allowing the invention to incorporate the knowledge gained from previous designs into current designs.

대표청구항 ▼

[ We claim:] [1.] A hierarchical adaptive system for emulating a process of designing integrated circuits and printed circuit boards comprising a tool manager, a schematic parser, a pseudo placement engine, a pseudo router, an electromagnetic translator, a schematic back annotator, and a shared info

[ We claim:] [1.] A hierarchical adaptive system for emulating a process of designing integrated circuits and printed circuit boards comprising a tool manager, a schematic parser, a pseudo placement engine, a pseudo router, an electromagnetic translator, a schematic back annotator, and a shared information database, whereina) said tool manager supervises and controls the storage and transfer of data,b) said schematic parser translates an electrical design schematic into a connectivity matrix wherein said electrical design schematic identifies components, properties of said components, pin connections and electrical interconnections,c) said pseudo placement section comprising fuzzy neural network determines routing channels, component size and placement using input data from said schematic parser, said tool manager, and said shared information database,d) said pseudo router section comprising fuzzy neural network generates a pin-to-pin routing,e) said electromagnetic translator section determines electromagnetic parameters from said routing channels, said component size and placement and said pin-to-pin routing,f) said schematic back annotator updates said electrical design schematic with said electromagnetic parameters, andg) said shared information database is accessible by said pseudo router, said pseudo placement section and said electromagnetic translator, and contains integrated circuit manufacturing and design data.