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Hierarchical adaptive state machine for emulating and augmenting software

국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판) G06F-015/18   
미국특허분류(USC) 706/050
출원번호 US-0841195 (1997-04-29)
발명자 / 주소
출원인 / 주소
대리인 / 주소
    Asmus
인용정보 피인용 횟수 : 92  인용 특허 : 10
초록
▼

The present invention defines a method for emulating an iterated process represented by a series of related tasks and a control mechanism that monitors and enables the iterative execution of those tasks until data associated with the process converges to predetermined goals or objectives. The invention defines a method in which fuzzy neural networks and discreet algorithms are applied to perform the process tasks and in which configurable, reloadable finite state machines are applied to control the execution of those tasks. In particular, the present inv...

대표
청구항
▼

[ We claim:] [1.] A hierarchical adaptive system for emulating a process of designing integrated circuits and printed circuit boards comprising a tool manager, a schematic parser, a pseudo placement engine, a pseudo router, an electromagnetic translator, a schematic back annotator, and a shared information database, whereina) said tool manager supervises and controls the storage and transfer of data,b) said schematic parser translates an electrical design schematic into a connectivity matrix wherein said electrical design schematic identifies components,...

이 특허에 인용된 특허 (10)

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  10. Yamanouchi Roy K. (San Jose CA) Covey D. Kevin (Sunnyvale CA) Schneider Sandra G. (San Jose CA). Structured logic design method using figures of merit and a flowchart methodology. USP1993115258919.

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