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Method for making semiconductor integrated circuit device having interconnection structure using tungsten film 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/4763
  • H01L-021/44
출원번호 US-0584065 (1996-01-11)
우선권정보 JP-0002551 (1995-01-11)
발명자 / 주소
  • Suzuki Masayuki,JPX
  • Nishihara Shinji,JPX
  • Sahara Masashi,JPX
  • Ishida Shinichi,JPX
  • Abe Hiromi,JPX
  • Tohda Sonoko,JPX
  • Uchiyama Hiroyuki,JPX
  • Tsugane Hideaki,JPX
  • Yoshiura Yoshiaki,JPX
출원인 / 주소
  • Hitachi Microcomputer System, Ltd., JPX
대리인 / 주소
    Antonelli, Terry, Stout & Kraus, LLP
인용정보 피인용 횟수 : 38  인용 특허 : 10

초록

A method for making a semiconductor integrated circuit device comprises the steps of: (a) depositing a first underlying film made of titanium nitride, on an insulating film having a plurality of through-holes; (b) depositing a tungsten film on the first underlying film, and etching the tungsten film

대표청구항

[ What is claimed is:] [1.] A method for making a semiconductor integrated circuit device, which comprises the steps of:(a) forming a first insulating film on a semiconductor substrate, the first insulating film having a plurality of first through-holes;(b) forming a tungsten film over said first in

이 특허에 인용된 특허 (10)

  1. Tomono Masami (Kokubunji JA) Abe Akira (Takasaki JA) Harada Seiki (Hachioji JA) Sato Kikuji (Kokubunji JA) Takagi Takeshi (Takasaki JA) Kamoshita Genichi (Koganei JA) Oya Yuichiro (Kodaira JA) Saiki , Discrete semiconductor device having polymer resin as insulator and method for making the same.
  2. Matsuura Megumi (Hyogo JPX) Ishida Tomohiro (Hyogo JPX), Manufacturing method of interconnection structure of semiconductor device.
  3. Hideshima Makoto (Tokyo JPX) Tsunoda Tetsujiro (Fujisawa JPX) Kojima Shinjiro (Chigasaki JPX) Ando Masaru (Kamakura JPX), Metal bump type semiconductor device and method for manufacturing the same.
  4. Marangon Maria S. (Naviglio ITX) Marmiroli Andrea (Alzano Lombardo ITX) Desanti Giorgio (Milan ITX), Metallization over tungsten plugs.
  5. Sun Shih W. (Austin TX) Lee Jen-Jiang (Austin TX), Method for device metallization by forming a contact plug and interconnect using a silicide/nitride process.
  6. Takahashi Kiyoshi (Tokyo JPX), Method for fabricating a gate electrode structure of compound semiconductor device.
  7. Shankar Krishna (Mountain View CA) Ramani Ram (San Jose CA), Multilayer interconnection for integrated circuit structure having two or more conductive metal layers.
  8. Avanzino Steven (Cupertino CA) Gupta Subhash (San Jose CA) Klein Rich (Mountain View CA) Luning Scott D. (Menlo Park CA) Lin Ming-Ren (Cupertino CA), Self aligned via dual damascene.
  9. Inoue Yasunori (Ohgaki JPX) Tsujimura Kazutoshi (Ohgaki JPX) Tanimoto Shinichi (Ohgaki JPX) Yamashita Yasuhiko (Hashima JPX) Yoneda Kiyoshi (Gifu-ken JPX) Ibara Yoshikazu (Gifu-ken JPX), Semiconductor device having cap-metal layer.
  10. Hibino Satoshi (Hamamatsu JPX) Kuwajima Tetsuya (Hamamatsu JPX), Wiring forming method.

이 특허를 인용한 특허 (38)

  1. Chien Wen-Cheng,TWX, Application of pure aluminum to prevent pad corrosion.
  2. Drexl, Stefan; Goebel, Thomas; Helneder, Johann; Hommel, Martina; Klein, Wolfgang; Kôrner, Heinrich; Mitchell, Andrea; Schwerd, Markus; Seck, Martin, Integrated connection arrangements.
  3. Xiao, De Yuan; Chen, Guo Qing, Method and system for forming conductive bumping with copper interconnection.
  4. Xiao, De Yuan; Chen, Guo Qing, Method and system for forming conductive bumping with copper interconnection.
  5. Xiao, De Yuan; Chen, Guo Qing, Method and system for forming conductive bumping with copper interconnection.
  6. H?gerl, J?rgen, Method for producing a semiconductor wafer, semiconductor chip, and intermediate semiconductor product.
  7. Uchiyama Hiroyuki,JPX ; Ogishima Atsushi,JPX ; Shukuri Shoji,JPX, Method of forming a MISFET device with a bit line completely surrounded by dielectric.
  8. Barr, Alexander L.; Venkatesan, Suresh; Clegg, David B.; Cole, Rebecca G.; Adetutu, Olubunmi; Greer, Stuart E.; Anthony, Brian G.; Venkatraman, Ramnath; Braeckelmann, Gregor; Reber, Douglas M.; Crown, Method of forming semiconductor device including interconnect barrier layers.
  9. Duesman, Kevin G.; Farnworth, Warren M., Method of forming semiconductor device utilizing die active surfaces for laterally extending die internal and external connections.
  10. Van De Goor, Albertus Theodorus Maria, Method of manufacturing a semiconductor device with metallization layers interconnected by tungsten plugs.
  11. Kumauchi, Takahiro; Yoshida, Makoto; Kajigaya, Kazuhiko, Method of manufacturing a semiconductor integrated circuit device.
  12. Smoak, Richard C., Method to improve the reliability of thermosonic gold to aluminum wire bonds.
  13. Ahn, Yongchul; Wong, Kaichiu, Methods of forming semiconductor structures, and articles and devices formed thereby.
  14. Domae, Shinichi; Masuda, Hiroshi; Kato, Yoshiaki; Yano, Kousaku, Multilayer wiring structure of semiconductor device, method of producing said multilayer wiring structure and semiconductor device to be used for reliability evaluation.
  15. Domae, Shinichi; Masuda, Hiroshi; Kato, Yoshiaki; Yano, Kousaku, Multilayer wiring structure of semiconductor device, method of producing said multilayer wiring structure and semiconductor device to be used for reliability evaluation.
  16. Domae, Shinichi; Masuda, Hiroshi; Kato, Yoshiaki; Yano, Kousaku, Multilayer wiring structure of semiconductor device, method of producing said multilayer wiring structure and semiconductor device to be used for reliability evaluation.
  17. Domae,Shinichi; Masuda,Hiroshi; Kato,Yoshiaki; Yano,Kousaku, Multilayer wiring structure of semiconductor device, method of producing said multilayer wiring structure and semiconductor device to be used for reliability evaluation.
  18. Domae,Shinichi; Masuda,Hiroshi; Kato,Yoshiaki; Yano,Kousaku, Multilayer wiring structure of semiconductor device, method of producing said multilayer wiring structure and semiconductor device to be used for reliability evaluation.
  19. Domae, Shinichi; Masuda, Hiroshi; Kato, Yoshiaki; Yano, Kousaku, Multilayer wiring structure of semiconductor device, method of producing said multilayer wiring structure and semiconductor to be used for reliability evaluation.
  20. Aoyagi, Takashi; Ogishima, Atsushi; Kobayashi, Hirotaka; Hara, Yuji, Process for multilayer wiring connections and bonding pad adhesion to dielectric in a semiconductor integrated circuit device.
  21. Uchiyama, Hiroyuki; Ogishima, Atsushi; Shukuri, Shoji, SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND THE PROCESS OF MANUFACTURING THE SAME HAVING POLY-SILICON PLUG, WIRING TRENCHES AND BIT LINES FORMED IN THE WIRING TRENCHES HAVING A WIDTH FINER THAN A PRE.
  22. Huber,Andreas; Gerstmeier,G��nter; Sommer,Michael Bernhard, Semiconductor chip with metallization levels, and a method for formation in interconnect structures.
  23. Moriya, Hiroshi; Iwasaki, Tomio; Miura, Hideo; Nishihara, Shinji; Sahara, Masashi, Semiconductor device and method of manufacturing the same.
  24. Moriya,Hiroshi; Iwasaki,Tomio; Miura,Hideo; Nishihara,Shinji; Sahara,Masashi, Semiconductor device and method of manufacturing the same.
  25. Toyosawa, Kenji; Ono, Atsushi; Chikawa, Yasunori; Sakaguchi, Nobuhisa; Nakamura, Nakae; Nakata, Yukinori, Semiconductor device having active element connected to an electrode metal pad via a barrier metal layer and interlayer insulating film.
  26. Suzuki Masayuki,JPX ; Nishihara Shinji,JPX ; Sahara Masashi,JPX ; Ishida Shinichi,JPX ; Abe Hiromi,JPX ; Tohda Sonoko,JPX ; Uchiyama Hiroyuki,JPX ; Tsugane Hideaki,JPX ; Yoshiura Yoshiaki,JPX, Semiconductor integrated circuit device and method for making the same.
  27. Suzuki, Masayuki; Nishihara, Shinji; Sahara, Masashi; Ishida, Shinichi; Abe, Hiromi; Tohda, Sonoko; Uchiyama, Hiroyuki; Tsugane, Hideaki; Yoshiura, Yoshiaki, Semiconductor integrated circuit device and method for making the same.
  28. Suzuki, Masayuki; Nishihara, Shinji; Sahara, Masashi; Ishida, Shinichi; Abe, Hiromi; Tohda, Sonoko; Uchiyama, Hiroyuki; Tsugane, Hideaki; Yoshiura, Yoshiaki, Semiconductor integrated circuit device and method for making the same.
  29. Suzuki, Masayuki; Nishihara, Shinji; Sahara, Masashi; Ishida, Shinichi; Abe, Hiromi; Tohda, Sonoko; Uchiyama, Hiroyuki; Tsugane, Hideaki; Yoshiura, Yoshiaki, Semiconductor integrated circuit device and method for making the same.
  30. Uchiyama, Hiroyuki; Ogishima, Atsushi; Shukuri, Shoji, Semiconductor integrated circuit device and the process of manufacturing the same for reducing the size of a memory cell by making the width of a bit line than a predetermined minimum size.
  31. Uchiyama,Hiroyuki; Ogishima,Atsushi; Shukuri,Shoji, Semiconductor integrated circuit device and the process of manufacturing the same having poly-silicon plug, wiring trenches and bit lines formed in the wiring trenches having a width finer than a pre.
  32. Duesman, Kevin G.; Farnworth, Warren M., Utilization of die active surfaces for laterally extending die internal and external connections.
  33. Duesman, Kevin G.; Farnworth, Warren M., Utilization of die active surfaces for laterally extending die internal and external connections.
  34. Duesman Kevin G. ; Farnworth Warren M., Utilization of die repattern layers for die internal connections.
  35. Duesman Kevin G. ; Farnworth Warren M., Utilization of die repattern layers for die internal connections.
  36. Duesman Kevin G. ; Farnworth Warren M., Utilization of die repattern layers for die internal connections.
  37. Matsunaga, Noriaki; Usui, Takamasa; Ito, Sachiyo, Wiring structure of semiconductor device.
  38. Matsunaga, Noriaki; Usui, Takamasa; Ito, Sachiyo, Wiring structure of semiconductor device.
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