초록 ▼

A method of forming a direct, copper-to-copper, connection between levels in an IC is disclosed. A via interconnection is formed by isotropically depositing a barrier material in a via through an insulator to a lower copper level, and then anisotropically etching the via to remove the barrier materi

A method of forming a direct, copper-to-copper, connection between levels in an IC is disclosed. A via interconnection is formed by isotropically depositing a barrier material in a via through an insulator to a lower copper level, and then anisotropically etching the via to remove the barrier material covering the lower copper level. The anisotropic etch leaves the barrier material lining the via through the insulator. The subsequently deposited upper metal level then directly contacts the lower copper level when the via is filled. A dual damascene interconnection is formed by etching an interconnection trench in an insulator and anisotropically depositing a non-conductive barrier material in the trench bottom. Then a via is formed from the trench interconnect to a lower copper level. As above, a conductive barrier material is isotropically deposited in the trench/via structure, and anisotropically etched to remove the barrier material covering the lower copper level. The insulating barrier material, lining the trench and via, remains. An IC via interconnection structure and a dual damascene interconnection structure, made in accordance with the above described methods, are also provided.

대표청구항 ▼

[ What is claimed is:] [10.] In an integrated circuit (IC) damascene interconnection trench, having sidewall surfaces and passing through a second thickness of the dielectric interlevel, exposing selected areas of a first thickness of the dielectric interlevel overlying a metal level, a method for f

[ What is claimed is:] [10.] In an integrated circuit (IC) damascene interconnection trench, having sidewall surfaces and passing through a second thickness of the dielectric interlevel, exposing selected areas of a first thickness of the dielectric interlevel overlying a metal level, a method for forming a dual damascene interconnect with sidewall barriers lining the trench and via, without forming an intervening barrier layer between the metal level and the dual damascene interconnect, the method comprising the following steps:a) anisotropically depositing an insulating barrier layer material overlying the trench, forming an insulating barrier layer overlying the selected areas of the dielectric interlevel first thickness where a via is subsequently formed;b) etching selected overlying areas of the insulating barrier layer and the underlying dielectric interlevel first thickness, exposing sidewall surfaces of the dielectric interlevel first thickness and selected areas of the metal level, whereby a via is formed from the trench to the metal level selected areas;c) conformally depositing a conductive barrier layer material overlying the trench and via, forming a conductive barrier layer on the sidewall surfaces of the dielectric interlevel first and second thicknesses and the metal level selected areas, whereby all the dual damascene surfaces are covered with the conductive barrier layer; andd) anisotropically etching, to selectively remove the conductive barrier layer overlying the metal level selected areas, exposing the metal level selected areas, but not the conductive barrier layer overlying the sidewall surfaces of the first dielectric interlevel first and second thicknesses, whereby a damascene process via and trench, having conductive barrier sidewall surfaces, are prepared to directly connect the metal level with a subsequently deposited copper metal level, without an intervening barrier layer, for improved conductivity.