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특허 상세정보

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내보내기 페이스북 공유 카카오톡 공유

Low resistance contact between integrated circuit metal levels and method for same

특허상세정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판) H01L-021/44   
미국특허분류(USC) 438/687 ; 438/622 ; 438/637 ; 438/638 ; 438/666 ; 438/672
출원번호 US-0896114 (1997-07-17)
발명자 / 주소
출원인 / 주소
대리인 / 주소
    Maliszewski
인용정보 피인용 횟수 : 202  인용 특허 : 3
초록
▼

A method of forming a direct, copper-to-copper, connection between levels in an IC is disclosed. A via interconnection is formed by isotropically depositing a barrier material in a via through an insulator to a lower copper level, and then anisotropically etching the via to remove the barrier material covering the lower copper level. The anisotropic etch leaves the barrier material lining the via through the insulator. The subsequently deposited upper metal level then directly contacts the lower copper level when the via is filled. A dual damascene inter...

대표
청구항
▼

[ What is claimed is:] [10.] In an integrated circuit (IC) damascene interconnection trench, having sidewall surfaces and passing through a second thickness of the dielectric interlevel, exposing selected areas of a first thickness of the dielectric interlevel overlying a metal level, a method for forming a dual damascene interconnect with sidewall barriers lining the trench and via, without forming an intervening barrier layer between the metal level and the dual damascene interconnect, the method comprising the following steps:a) anisotropically deposi...

이 특허에 인용된 특허 (3)

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  2. Avanzino Steven (Cupertino CA) Gupta Subhash (San Jose CA) Klein Rich (Mountain View CA) Luning Scott D. (Menlo Park CA) Lin Ming-Ren (Cupertino CA). Dual damascene with a protective mask for via etching. USP1997115686354.
  3. Shoda Naohiro (Wappingers Falls NY). Method of forming studs and interconnects in a multi-layered semiconductor device. USP1996065529953.

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