초록 ▼

A transaction ordering mechanism for processor-based computing systems ensures proper ordering of transactions between the processor, I/O and memory subsystems, ensures cache coherence within the computing system, and facilitates concurrence of the transactions so as to enable high-bandwidth, deadlo

A transaction ordering mechanism for processor-based computing systems ensures proper ordering of transactions between the processor, I/O and memory subsystems, ensures cache coherence within the computing system, and facilitates concurrence of the transactions so as to enable high-bandwidth, deadlock-free operation. I/O to memory transactions and processor to memory transactions are placed in a memory request queue in the order in which such transactions appear on the processor bus; I/O to memory transactions are placed in an inbound request queue in the order such transactions appear on the I/O bus; and processor to I/O transactions and completions corresponding to split-transaction I/O to memory read transactions are placed in an outbound request queue in the order in which the split-transaction I/O to memory read transactions and the processor to I/O transactions appear on the processor bus.

대표청구항 ▼

[ What is claimed is:] [9.] In a processor-based computing system, an apparatus for ordering I/O to memory transactions relative to processor to memory transactions and processor to I/O transactions, the I/O to memory transactions including I/O to memory read transactions, each having an associated

[ What is claimed is:] [9.] In a processor-based computing system, an apparatus for ordering I/O to memory transactions relative to processor to memory transactions and processor to I/O transactions, the I/O to memory transactions including I/O to memory read transactions, each having an associated completion, the apparatus comprising:(A) a processor bus;(B) an I/O bus; and(C) a memory-I/O controller coupled between the processor bus and the I/O bus, the memory-I/O controller including:(1) an inbound request queue coupled between the I/O bus and the processor bus;(2) an outbound request queue coupled between the processor bus and the I/O bus;(3) a memory request queue, coupled to the processor bus; and(4) a transaction ordering flow controller, coupled to the processor bus, the I/O bus, the inbound request queue, the outbound request queue, and the memory request queue, which controls placement of inbound transactions in the inbound request queue in the order these transactions appear on the I/O bus, controls placement of I/O to memory and processor to memory transactions in the memory request queue in the order these transactions appear on the processor bus, and controls placement of processor to I/O transactions and completions associated with I/O to memory read transactions in the outbound queue in the order such transactions appear on the processor bus.