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Physical design automation system and process for designing integrated circuit chips using highly parallel sieve optimi 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-017/50
출원번호 US-0560848 (1995-11-20)
발명자 / 주소
  • Scepanovic Ranko
  • Koford James S.
  • Kudryavtsev Valeriy B.,RUX
  • Andreev Alexander E.,RUX
  • Aleshin Stanislav V.,RUX
  • Podkolzin Alexander S.,RUX
  • Roseboom Edward M.
출원인 / 주소
  • LSI Logic Corporation
대리인 / 주소
    Mitchell, Silberberg & Knupp LLP
인용정보 피인용 횟수 : 23  인용 특허 : 7

초록

A process for implementation on a programmed digital computer includes providing a placement of clusters of cells which are assigned to regions on an integrated circuit chip, and combining the regions to form region groups. The region groups collectively constitute a "jiggle" which resembles a sieve

대표청구항

[ We claim:] [1.] A process for designing an integrated circuit chip, comprising the steps of:(a) providing a placement of clusters of cells, each cluster being assigned to one of plural predefined and non-overlapping regions on the chip;(b) combining the pre-defined and non-overlapping regions to f

이 특허에 인용된 특허 (7)

  1. Moore Wesley (Morrisville NC) Huffman Ward (Durham NC), Hierarchical floorplanner for gate array design layout.
  2. Ding Cheng-Liang (San Jose CA) Ho Ching-Yen (Saratoga CA), Integrated circuit cell placement using optimization-driven clustering.
  3. Rostoker Michael D. (Boulder Creek CA) Koford James S. (San Jose CA) Jones Edwin R. (Sunnyvale CA) Boyle Douglas B. (Palo Alto CA) Scepanovic Ranko (Cupertino CA), Integrated circuit physical design automation system utilizing optimization process decomposition and parallel processin.
  4. Gould Elliot L. (Colchester VT) Kemerer Douglas W. (Essex Junction VT) McAllister Lance A. (Williston VT) Piro Ronald A. (South Burlington VT) Richardson Guy R. (Milton VT) Wellburn Deborah A. (Colch, Method of combining gate array and standard cell circuits on a common semiconductor chip.
  5. Scepanovic Ranko (San Jose CA) Koford James S. (San Jose CA) Kudryavtsev Valeriy B. (Moscow RUX) Andreev Alexander E. (Moskovskaja Oblast RUX) Aleshin Stanislav V. (Moscow RUX) Podkolzin Alexander S., Physical design automation system and process for designing integrated circuit chips using multiway partitioning with co.
  6. Webb Michael C. (Exton PA), Secondary containment system using flexible piping.
  7. Aneha Nobuhiko (Kawasaki JPX) Baba Shigenori (Yokohama JPX), Semiconductor integrated circuit having overlapping circuit cells and method for designing circuit pattern therefor.

이 특허를 인용한 특허 (23)

  1. Padalia, Ketan; Ludwin, Adrian; Fung, Ryan; Betz, Vaughn, Apparatus and associated methods for parallelizing clustering and placement.
  2. Kazuhiro Takahashi JP, Cell-layout method in integrated circuit devices.
  3. Igusa Mitsuru ; Chen Hsi-Chuan ; Chao Shiu-Ping ; Dai Wei-Jin ; Shyong Daw Yang, Design hierarchy-based placement.
  4. Bruce Pedersen ; Francis B. Heile ; Marwan Adel Khalaf ; David Wolk Mendel, Generation of sub-netlists for use in incremental compilation.
  5. Datta Ray,Partha P.; Grinchuk,Mikhail I.; Raspopovic,Pedja, Method and apparatus for adaptive timing optimization of an integrated circuit design.
  6. Raspopovic Pedja ; Scepanovic Ranko ; Andreev Alexander E., Method and apparatus for coarse global routing.
  7. Mendel David Wolk, Method and apparatus for contemporaneously compiling an electronic circuit design by contemporaneously bipartitioning the electronic circuit design using parallel processing.
  8. Scepanovic Ranko ; Andreev Alexander E. ; Gasanov Elyar E.,RUX ; Raspopovic Pedja, Method and apparatus for hierarchical global routing descend.
  9. Igarashi, Shunji; Koike, Kazunori, Method and apparatus for modifying flattened data of designed circuit pattern.
  10. Dotson, Michael W.; DeGroff Drumm, Anthony; Ma, Dazhuang J.; Puri, Ruchir; Trevillyan, Louise H., Method and apparatus for parallel processing of semiconductor chip designs.
  11. Chong, Philip; Szegedy, Christian, Method and system for approximate placement in electronic designs.
  12. Pai, Ravi R.; Pereira, Mark; Bhat, Nitin P, Method and system for processing geometrical layout design data.
  13. Tang,Xiaoping, Method and system to redistribute white space for minimizing wire length.
  14. Boyle Douglas B. ; Koford James S., Method for providing performance-driven logic optimization in an integrated circuit layout design.
  15. Watanabe, Susumu, Method of designing integrated circuit and apparatus for designing integrated circuit.
  16. Watanabe,Susumu, Method of designing integrated circuit and apparatus for designing integrated circuit.
  17. Majid Sarrafzadeh ; Lawrence Pileggi ; Sharad Malik ; Feroze Peshotan Taraporevala ; Abhijeet Chakraborty ; Gary K. Yeap ; Salil R. Raje ; Lilly Shieh ; Douglas B. Boyle ; Dennis Yamamoto, Placement method for integrated circuit design using topo-clustering.
  18. Sarrafzadeh, Majid; Pileggi, Lawrence; Malik, Sharad; Taraporevala, Feroze Peshotan; Chakraborty, Abhijeet; Yeap, Gary K.; Raje, Salil R.; Shieh, Lilly; Boyle, Douglas B.; Yamamoto, Dennis, Placement method for integrated circuit design using topo-clustering.
  19. Sarrafzadeh, Majid; Raje, Salil R., Placement method for integrated circuit design using topo-clustering.
  20. Lin, Pole Shang; Wen, Kuei Shan; Perng, Ruey Kuen, Simulation of circuits with repetitive elements.
  21. Tcherniaev, Andrei; Feinberg, Iouri; Chan, Walter; Tuan, Jeh-Fu; Deng, An-Chang, Transistor level circuit simulator using hierarchical data.
  22. Ray, Partha P. Data; Grinchuk, Mikhail I.; Raspopovic, Pedja, Virtual tree-based netlist model and method of delay estimation for an integrated circuit design.
  23. Alexander Andreev ; Ivan Pavisic ; Pedja Raspopovic, Wire routing optimization.
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