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Method for fabricating a semiconductor device having a refractory metal pillar for electrical connection 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/28
  • H01L-021/311
출원번호 US-0769162 (1996-12-18)
우선권정보 JP-0329303 (1995-12-18)
발명자 / 주소
  • Yamada Yoshiaki,JPX
출원인 / 주소
  • NEC Corporation, JPX
대리인 / 주소
    Hayes, Soloway, Hennessey, Grossman & Hage, P.C.
인용정보 피인용 횟수 : 73  인용 특허 : 5

초록

Disclosed is a method for fabricating a semiconductor device which prevents generation of imperfections in an aluminum alloy as an upper wiring even when part of a refractory metal pillar, which fills in a contact hole connecting lower and upper wiring layers, is exposed due to displacement of the u

대표청구항

[ What is claimed is:] [1.] A method for fabricating a semiconductor device, said method comprising the steps of:forming a first insulation film on a first wiring layer formed on a semiconductor substrate;forming a second insulation film on said first insulation film;forming a third insulation film

이 특허에 인용된 특허 (5)

  1. Chen Kuang-Chao (Taipei TWX) Hsia Shaw-Tzeng (Taipei TWX), Blanket tungsten etchback process using disposable spin-on-glass.
  2. Dennison Charles H. (Boise ID) Blalock Guy T. (Boise ID), Method for making electrical contact with an active area through sub-micron contact openings and a semiconductor device.
  3. Zhao Bin, Method of making a damascene metallization.
  4. Nishiyama Yukio (Yokohama JPX) Nakata Rempei (Kawasaki JPX) Hayasaka Nobuo (Yokosuka JPX) Okano Haruo (Tokyo JPX) Aoki Riichirou (Tokyo JPX) Nagamatsu Takahito (Kawasaki JPX) Satoh Akemi (Sagamihara , Method of manufacturing silicon oxide film containing fluorine.
  5. Mu Xiao-Chun (Saratoga CA) Sivaram Srinivasan (San Jose CA) Gardner Donald S. (Mountain View CA) Fraser David B. (Danville CA), Methods of forming an interconnect on a semiconductor substrate.

이 특허를 인용한 특허 (73)

  1. Zhu,Wenxian; Yu,Jengyi; Sutanto,Siswanto; Sun,Pingsheng; Lowe,Jeffrey Chih Hou; Fung,Waikit; Poon,Tze Wing, Biased Hetch process in deposition-etch-deposition gap fill.
  2. Lee, Jin-Yuan; Lin, Mou-Shiung; Huang, Ching-Cheng, Chip structure and process for forming the same.
  3. Lee, Jin-Yuan; Lin, Mou-Shiung; Huang, Ching-Cheng, Chip structure and process for forming the same.
  4. Lin, Mou-Shiung; Lee, Jin-Yuan; Huang, Ching-Cheng, Chip structure and process for forming the same.
  5. Lin, Mou-Shiung; Lee, Jin-Yuan; Huang, Ching-Cheng, Chip structure and process for forming the same.
  6. Papasouliotis,George D.; Goldner,Edith; Gauri,Vishal; Rahman,Md Sazzadur; Singh,Vikram, Deposition profile modification through process chemistry.
  7. Wesley Natzle ; Richard A. Conti ; Laertis Economikos ; Thomas Ivers ; George D. Papasouliotis, Directional CVD process with optimized etchback.
  8. Papasouliotis,George D.; Bayman,Atiye, Dynamic modification of gap fill process characteristics.
  9. Bayman,Atiye; Rahman,Md Sazzadur; Zhang,Weijie; van Schravendijk,Bart; Gauri,Vishal; Papasouliotis,George D.; Singh,Vikram, Gap fill for high aspect ratio structures.
  10. Nguyen,Minh Anh; Lang,Chi I; Zhu,Wenxian; Huang,Judy H., Halogen-free noble gas assisted Hplasma etch process in deposition-etch-deposition gap fill.
  11. Lang,Chi I; Zhu,Wenxian; Limdulpaiboon,Ratsamee; Huang,Judy H., Helium-based etch process in deposition-etch-deposition gap fill.
  12. Lin, Mou-Shing, High performance system-on-chip using post passivation process.
  13. Lin, Mou-Shiung, High performance system-on-chip using post passivation process.
  14. Shanker,Sunil; Cox,Sean; Lang,Chi I; Huang,Judy H.; Nguyen,Minh Anh; Vo,Ken; Zhu,Wenxian, Hydrogen treatment enhanced gap fill.
  15. Hui Angela T. ; Chen Hung-Sheng ; Kim Unsoon, Method and system for providing a contact on a semiconductor device.
  16. Sutanto,Siswanto; Zhu,Wenxian; Fung,Waikit; Lim,Mayasari; Gauri,Vishal; Papasouliotis,George D., Method for controlling etch process repeatability.
  17. Skala Stephen L. ; Bothra Subhas, Method for encapsulating a metal via in damascene.
  18. Lin, Mou-Shiung; Lee, Jin-Yuan; Huang, Ching-Cheng, Method for fabricating circuitry component.
  19. Wang,Kae Horng; Staub,Ralf; Kr철nke,Matthias, Method for fabricating contacts for integrated circuits, and semiconductor component having such contacts.
  20. Papasouliotis, George D.; Tas, Robert D., Method of chemical modification of structure topography.
  21. Yeh Wen-Kuan,TWX ; Lin Tony,TWX ; Huang Heng-Sheng,TWX, Method of fabricating a barrier layer.
  22. Cleeves, James M., Method of making a contact and via structure.
  23. Kraft, Jochen; Rohracher, Karl; Schrems, Martin, Method of producing a semiconductor device with protruding contacts.
  24. Bombardier, Susan G.; Feeney, Paul M.; Geffken, Robert M.; Horak, David V.; Rutten, Matthew J., Method of reducing planarization defects.
  25. Burke, Chad M.; Li, Baozhen; Wong, Keith Kwong Hon; Yang, Chih-Chao, Method to improve fine Cu line reliability in an integrated circuit device.
  26. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
  27. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
  28. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
  29. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
  30. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
  31. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
  32. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chips.
  33. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation method for semiconductor chip or wafer.
  34. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation structure for semiconductor chip or wafer.
  35. Bronner Gary B. ; Gambino Jeffrey P., Process for controlling the height of a stud intersecting an interconnect.
  36. Bayman,Atiye; Papasouliotis,George D.; Ling,Yong; Zhang,Weijie; Gauri,Vishal; Lim,Mayasari, Process modulation to prevent structure erosion during gap fill.
  37. Ping-Chuan Wang ; Ronald G. Filippi ; Robert D. Edwards ; Edward W. Kiewra ; Roy C. Iggulden, Process of enclosing via for improved reliability in dual damascene interconnects.
  38. van Schravendijk, Bart; Hill, Richard S.; van den Hoek, Wilbert; te Nijenhuis, Harald, Protective layer to enable damage free gap fill.
  39. Lang,Chi i; Limdulpaiboon,Ratsamee; Gonzalez,Cayetano, Strain engineering--HDP thin film with tensile stress for FEOL and other applications.
  40. Yu,Jengyi; Lang,Chi I; Huang,Judy H., Stress profile modulation in STI gap fill.
  41. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  42. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  43. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  44. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  45. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  46. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  47. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  48. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  49. Lin, Mou-Shiung; Lee, Jin-Yuan, Top layers of metal for high performance IC's.
  50. Lin, Mou-Shiung; Lee, Jin-Yuan, Top layers of metal for high performance IC's.
  51. Lin, Mou-Shiung; Lee, Jin-Yuan, Top layers of metal for high performance IC's.
  52. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  53. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  54. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  55. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  56. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  57. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  58. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  59. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  60. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  61. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  62. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  63. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  64. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  65. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  66. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  67. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  68. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  69. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  70. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  71. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  72. Mou-Shiung Lin TW, Top layers of metal for high performance IC's.
  73. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Top layers of metal for integrated circuits.
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