$\require{mediawiki-texvc}$
  • 검색어에 아래의 연산자를 사용하시면 더 정확한 검색결과를 얻을 수 있습니다.
  • 검색연산자
검색연산자 기능 검색시 예
() 우선순위가 가장 높은 연산자 예1) (나노 (기계 | machine))
공백 두 개의 검색어(식)을 모두 포함하고 있는 문서 검색 예1) (나노 기계)
예2) 나노 장영실
| 두 개의 검색어(식) 중 하나 이상 포함하고 있는 문서 검색 예1) (줄기세포 | 면역)
예2) 줄기세포 | 장영실
! NOT 이후에 있는 검색어가 포함된 문서는 제외 예1) (황금 !백금)
예2) !image
* 검색어의 *란에 0개 이상의 임의의 문자가 포함된 문서 검색 예) semi*
"" 따옴표 내의 구문과 완전히 일치하는 문서만 검색 예) "Transform and Quantization"

특허 상세정보

Method and system for layout and schematic generation for heterogeneous arrays

국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판) H03K-019/177    H03K-007/38   
미국특허분류(USC) 326/041 ; 326/039 ; 326/038
출원번호 US-0968543 (1997-11-12)
발명자 / 주소
출원인 / 주소
대리인 / 주소
    Heslin & Rothenberg, P.C.
인용정보 피인용 횟수 : 67  인용 특허 : 12
초록

A method and system for defining, placing and routing kernels for a family of integrated circuits is provided. The integrated circuits are defined using repeatable row and column circuit types. Kernels are defined by the intersections of the row and column circuit types in the array. The kernels are placed and routed automatically for each member of the family of integrated circuit arrays, each member being generally characterized by a different size, i.e., a different number of repeatable row or column circuit types.

대표
청구항

[ What is claimed is:] [1.] An architecture for a family of differently sized programmable arrays, each member of the family having a plurality of logic cells and support circuitry therein, the logic cells being arranged in four sections, the support circuitry being generally distributed throughout a cruciform-shaped region generally centered in the array which defines the four sections of logic cells therein, such that the length of the arms of the cruciform and the sizes of the sections can be together varied to produce the differently sized members of...

이 특허에 인용된 특허 (12)

  1. McElroy David J. (Houston TX). EPROM and RAM cell layout with equal pitch for use in fault tolerant memory device or the like. USP1983074393474.
  2. McGowan John E. ; Plants William C. ; Landry Joel D. ; Kaptanoglu Sinan ; Miller Warren K.. Flexible, high-performance static RAM architecture for field-programmable gate arrays. USP1998045744980.
  3. Hatano Tsutomu (Tokyo JPX). Gate array semiconductor integrated circuit device. USP1992065119158.
  4. Heath Herbert E. (Los Angeles CA) Block Jay M. (Thousand Oaks CA). Hierarchical configurable gate array. USP1987084688072.
  5. Seefeldt David F. (Palm Bay FL) Iacoponi Michael J. (Indian Harbor Beach FL) Vail ; Jr. David K. (Palm Bay FL). Hierarchical variable die size gate array architecture. USP1990124978633.
  6. Huang Joseph ; Cliff Richard G. ; Reddy Srinivas T.. Input/output interface circuitry for programmable logic array integrated circuit devices. USP1998065764080.
  7. Shimizu Atsushi (Ome JPX) Isomura Satoru (Ome MA JPX) Yamada Takeo (Boston MA) Kobayashi Tohru (Iruma JPX) Fujimura Yoshuhiro (Ome JPX) Ito Yuko (Ome JPX). Integrated circuit having alternate rows of logic cells and I/O cells. USP1994085341049.
  8. Kawai Hideki (Nara JPX) Fujii Masaru (Takatsuki JPX) Ohta Kiyoto (Takatsuki JPX) Maeyama Yoshikazu (Kyoto JPX). Layout for stable high speed semiconductor memory device. USP1989014796224.
  9. McClintock Cameron ; Cliff Richard G. ; Leong William. Programmable logic array integrated circuits with segmented, selectively connectable, long interconnection conductors. USP1998015705939.
  10. Camarota Rafael C. (San Jose CA) Furtek Frederick C. (Menlo Park CA) Ho Walford W. (Saratoga CA) Browder Edward H. (Saratoga CA). Programmable logic cell and array. USP1992095144166.
  11. Stansfield Anthony I. (Hotwells GBX). Programmable logic device with memory that can store routing data of logic data. USP1995125473267.
  12. Kean Thomas A.,GB6. Programmable switch for FPGA input/output signals. USP1998015705938.

이 특허를 인용한 특허 피인용횟수: 67

  1. Ramchandran, Amit. Adaptable datapath for a digital processing system. USP2013028380884.
  2. Ramchandran, Amit. Adaptable datapath for a digital processing system. USP2015049015352.
  3. Ramchandran, Amit. Adaptable datapath for a digital processing system. USP2014048706916.
  4. Ramchandran, Amit. Adaptable datapath for a digital processing system. USP2009107606943.
  5. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J.. Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements. USP2015109164952.
  6. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J.. Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements. USP2013098543795.
  7. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James. Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements. USP2013098533431.
  8. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James. Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements. USP2011088010593.
  9. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James. Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements. USP2011067962716.
  10. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James. Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements. USP2004126836839.
  11. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James. Adaptive integrated circuitry with heterogenous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements. USP2013098543794.
  12. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James. Adaptive processor for performing an operation with simple and complex units each comprising configurably interconnected heterogeneous elements. USP2013018356161.
  13. Master, Paul L.; Uvacek, Bohumir. Apparatus and method for adaptive multimedia reception and transmission in communication environments. USP2015049002998.
  14. Master, Paul L.; Smith, Stephen J.; Watson, John. Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements. USP2016059330058.
  15. Master, Paul L.; Smith, Stephen J.; Watson, John. Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements. USP2014118880849.
  16. Master, Paul L.; Smith, Stephen J.; Watson, John. Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements. USP2012088250339.
  17. Master,Paul L.; Smith,Stephen J.; Watson,John. Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements. USP2006016986021.
  18. Master, Paul L.; Smith, Stephen J.; Watson, John. Apparatus, system and method for configuration of adaptive integrated circuitry having fixed, application specific computational elements. USP2017039594723.
  19. Master, Paul L.; Smith, Stephen J.; Watson, John. Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements. USP2013048412915.
  20. Master, Paul L.; Smith, Stephen J.; Watson, John. Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements. USP2012078225073.
  21. Hogenauer, Eugene B.. Arithmetic node including general digital signal processing functions for an adaptive computing machine. USP2015028949576.
  22. Howard, Ric; Katragadda, Ramana V.. Asynchronous, independent and multiple process shared memory system in an adaptive computing architecture. USP2009087577799.
  23. de Waal, Abraham B.; Diard, Franck R.. Automatic quality testing of multimedia rendering by software drivers. USP2011077987065.
  24. Heidari, Ghobad; Chang, Kuor Hsin; Master, Paul L.; Hogenauer, Eugene B.; Scheuermann, Walter James. Communications module, device, and method for implementing a system acquisition function. USP2009117620097.
  25. Master, Paul L.; Watson, John. Configurable hardware based digital imaging apparatus. USP2009107609297.
  26. Rubin, Owen Robert; Murray, Eric; Uhrig, Nalini Praba. Consumer product distribution in the embedded system market. USP2010017644279.
  27. Scheuermann, W. James; Hogenauer, Eugene B.. Control node for multi-core system. USP20190110185502.
  28. Furtek, Frederick Curtis; Master, Paul L.. External memory controller. USP2012098266388.
  29. Furtek, Frederick Curtis; Master, Paul L.. External memory controller node. USP2014078769214.
  30. Furtek, Fredrick Curtis; Master, Paul L.. External memory controller node. USP2011077984247.
  31. Furtek, Fredrick Curtis; Master, Paul L.. External memory controller node. USP2011077979646.
  32. Scheuermann,Walter James. Hardware implementation of the secure hash standard. USP2009027489779.
  33. Scheuermann, W. James; Hogenauer, Eugene B.. Hardware task manager. USP2017059665397.
  34. Scheuermann, W. James; Hogenauer, Eugene B.. Hardware task manager. USP2012068200799.
  35. Scheuermann, W. James; Hogenauer, Eugene B.. Hardware task manager. USP2010017653710.
  36. Scheuermann, W. James; Hogenauer, Eugene B.. Hardware task manager. USP2014078782196.
  37. Stephen L. Wasson. Heterogeneous programmable gate array. USP2002086433578.
  38. Master,Paul L.; Hogenauer,Eugene; Scheuermann,Walter James. Hierarchical interconnect for configuring separate interconnects for each group of fixed and diverse computational elements. USP2008017325123.
  39. Iwasa, Yoshiro. Input/output cell placement method and semiconductor device. USP2004046721933.
  40. Furtek, Frederick Curtis; Master, Paul L.; Plunkett, Robert Thomas. Input/output controller node in an adaptable computing environment. USP2009117624204.
  41. Heidari-Bateni, Ghobad; Sambhwani, Sharad D.. Internal synchronization control for adaptive integrated circuitry. USP2012108296764.
  42. Sambhwani, Sharad; Heidari, Ghobad. Low I/O bandwidth method and system for implementing detection and identification of scrambling codes. USP2013058442096.
  43. Sambhwani, Sharad; Heidari, Ghobad. Low I/O bandwidth method and system for implementing detection and identification of scrambling codes. USP2010027668229.
  44. Sambhwani,Sharad; Heidari,Ghobad. Low I/O bandwidth method and system for implementing detection and identification of scrambling codes. USP2009037512173.
  45. Master, Paul L.. Method and system for achieving individualized protected space in an operating system. USP2010027660984.
  46. Master, Paul L.. Method and system for creating and programming an adaptive computing engine. USP2011017865847.
  47. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L.. Method and system for managing hardware resources to implement system functions using an adaptive computing architecture. USP2015059037834.
  48. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L.. Method and system for managing hardware resources to implement system functions using an adaptive computing architecture. USP2016079396161.
  49. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L.. Method and system for managing hardware resources to implement system functions using an adaptive computing architecture. USP2013118589660.
  50. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L.. Method and system for managing hardware resources to implement system functions using an adaptive computing architecture. USP2010077752419.
  51. Scheuermann, W. James. Method and system for reconfigurable channel coding. USP2014078767804.
  52. Scheuermann, W. James. Method and system for reconfigurable channel coding. USP2012088249135.
  53. Scheuermann, W. James. Method and system for reconfigurable channel coding. USP2010107809050.
  54. Scheuermann, W. James. Method and system for reconfigurable channel coding. USP2010107822109.
  55. Master, Paul L.; Scheuermann, W. James. Method and system for reducing the time-to-market concerns for embedded system design. USP2009117620678.
  56. Altfeld,Helge; Gsch철derer,Monika; Eisenhut,Michael; Walter,Marc; Frankowsky,Beate. Method for fabricating an integrated semiconductor circuit. USP2006027007260.
  57. Master,Paul L.; Hogenauer,Eugene; Wu,Bicheng William; Chuang,Dan MingLun; Freeman Benson,Bjorn. Method, system and program for developing and scheduling adaptive integrated circuity and corresponding control or configuration information. USP2009017478031.
  58. Scheuermann,W. James. Processing architecture for a reconfigurable arithmetic node. USP2008107433909.
  59. Master, Paul L.. Profiling of software and circuit designs utilizing data operation analyses. USP2012098276135.
  60. Master, Paul L.; Murray, Eric; Mehegan, Joseph; Plunkett, Robert Thomas. Secure storage of program code for an embedded system. USP2010097802108.
  61. Master,Paul L.; Watson,John. Storage and delivery of device features. USP2009027493375.
  62. Jacob,Rojit; Chuang,Dan Minglun. System and method using embedded microprocessor as a node in an adaptable computing machine. USP2009037502915.
  63. Master, Paul L.; Watson, John. System for adapting device standards after manufacture. USP2009107602740.
  64. Master, Paul L.; Watson, John. System for authorizing functionality in adaptable hardware devices. USP201109E042743.
  65. Hung,Lup Cheong Patrick; Kao,John; Sung,Frank; Chen,Yu Jen; Liou,Edwin D.; Chen,Ming Hsin Thomas; Liou,Jeffrey; Shen,Yu Yong; Chen,Chun Cho. System, method, and user interface providing customized document portfolio management. USP2008067386539.
  66. Katragadda, Ramana; Spoltore, Paul; Howard, Ric. Task definition for specifying resource requirements. USP2012018108656.
  67. Cline, Ronald L.. Very fine grain field programmable gate array architecture and circuitry. USP2003026525561.