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Method of forming an integrated circuit including filling and planarizing a trench having an oxygen barrier layer 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/62
출원번호 US-0800012 (1997-02-13)
발명자 / 주소
  • Razouk Reda R.
  • Egan Kulwant S.
  • Yindeepol Wipawan
  • Koscielniak Waclaw C.
출원인 / 주소
  • National Semiconductor Corporation
대리인 / 주소
    Skjerven, Morrill, MacPherson, Franklin, & Friel L.L.P.Chambers
인용정보 피인용 횟수 : 17  인용 특허 : 12

초록

A trench which has walls intersecting a surface of a semiconductor substrate and an oxidation/diffusion barrier layer lining the walls is disclosed. The oxidation/diffusion barrier extends over the edges of the trench to prevent, for example, stress defects in the trench corners and vertical bird's

대표청구항

[ What is claimed is:] [1.] A method of filling an orifice disposed in a wafer and having an orifice opening onto a surface of the wafer, wherein the wafer surface is external to the orifice, the method comprising the steps of:forming an oxygen diffusion barrier within the orifice and over the wafer

이 특허에 인용된 특허 (12)

  1. Tateoka Hidehisa (Tenri JPX) Onishi Shigeo (Nara JPX) Tanaka Kenichi (Nara JPX), Method of forming an element isolating portion in a semiconductor device.
  2. Razouk Reda (Sunnyvale CA), Method of inducing flow or densification of phosphosilicate glass for integrated circuits.
  3. El-Kareh Badih (South Hero VT) Garnache Richard R. (Shelburne VT) Ghatalia Ashwin K. (Hopewell Junction NY), Method of making a contact to a trench isolated device.
  4. Aoki Masami (Kanagawa JPX) Takato Hiroshi (Kanagawa JPX), Method of manufacturing a semiconductor device isolated by a trench.
  5. Hillenius Steven J. (Summit NJ) Lynch William T. (Summit NJ) Manchanda Lalita (New Providence NJ) Pinto Mark R. (Morristown NJ) Vaidya Sheila (Watchung NJ), Planar isolation technique for integrated circuits.
  6. Kawaji Mikinori (Hino JPX) Takakura Toshihiko (Koganei JPX) Uchida Akihisa (Koganei JPX) Kuroda Shigeo (Ome JPX) Tamaki Yoichi (Kokubunji JPX) Shiba Takeo (Kodaira JPX) Sagara Kazuhiko (Tokyo JPX) Ka, Process of manufacturing semiconductor integrated circuit device and product formed thereby.
  7. Okada Daisuke (Koganei JPX) Uchida Akihisa (Koganei JPX) Takakura Toshihiko (Koganei JPX) Nakashima Shinji (Koganei JPX) Ohno Nobuhiko (Tokorozawa JPX) Ogiue Katsumi (Hinode JPX), Semiconductor body, and device formed therefrom, having grooves with silicon nitride on the groove surfaces.
  8. Kishi Shuji (Tokyo JPX), Semiconductor device having U-groove.
  9. Lee Kuo-Hua (Lehigh County PA) Lu Chih-Yuan (Lehigh County PA), Semiconductor device manufacture including trench formation.
  10. Takemura Hisashi (Tokyo JPX) Sugiyama Mitsuhiro (Tokyo JPX), Semiconductor device with insulating isolation groove.
  11. Tamaki Yoichi (Kokubunji JPX) Kure Tokuo (Kokubunji JPX) Sato Akira (Hachioji JPX) Higuchi Hisayuki (Kokubunji JPX), Tapered groove IC isolation.
  12. Rogers Steven H. (Midwest City OK) Mundt Randall S. (Colorado Springs CO) Kaya Denise A. (Woodland Park CO), Trench isolation structures.

이 특허를 인용한 특허 (17)

  1. William F. Cantarini ; Steven C. Lizotte, Integrated photovoltaic switch with integrated power device including etching backside of substrate.
  2. Ibok Effiong E., Isotropic assisted dual trench etch.
  3. Hoilien, Noel, Locos nitride capping of deep trench polysilicon fill.
  4. Yu, Ho-Yuan, Method and structure for composite trench fill.
  5. Chen Coming,TWX ; Lin Tony,TWX, Method for fabricating an isolation structure including a shallow trench isolation structure and a local-oxidation isolation structure.
  6. Fisher, Philip; Chan, Darin A., Method for shallow trench isolation with removal of strained island edges.
  7. Gogoi, Bishnu P.; Roop, Raymond M.; Desai, Hemant D., Method of forming a seal for a semiconductor device.
  8. Ishikawa Hiraku,JPX, Method of manufacturing isolation trenches using silicon nitride liner.
  9. Ahn, Dong-Ho; Kang, Ho-Kyu; Bae, Geum-Jong, Method of preventing semiconductor layers from bending and semiconductor device formed thereby.
  10. Lin Ping-Wei,TWX ; Kao Ming-Kuan,TWX ; Li Jui-Ping,TWX, Method to prevent the formation of a thinner portion of insulating layer at the junction between the side walls and the bottom insulator.
  11. Bourdelle, Konstantin; Mazure, Carlos, Methods for manufacturing multilayer wafers with trench structures.
  12. Sayama Hirokazu,JPX ; Kuroi Takashi,JPX ; Sakai Maiko,JPX ; Horita Katsuyuki,JPX, Semiconductor device and method of fabricating thereof.
  13. Ryuichi Okamura JP, Semiconductor device having improved pad coupled to wiring on semiconductor substrate.
  14. Foote, Jr., Richard W., System and method for creating different field oxide profiles in a locos process.
  15. Dark, Charles A., System and method for providing a nitride cap over a polysilicon filled trench to prevent formation of a vertical bird's beak structure in the manufacture of a semiconductor device.
  16. Chung, Yifu; Chang, Leon; Lin, Ping-Wei, Trench gate oxide formation method.
  17. Raaijmakers,Ivo; Soininen,Pekka T.; Granneman,Ernst H. A., Trench isolation structures for integrated circuits.
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