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Synchronizing clock pulse generator for logic derived clock signals with synchronous clock suspension capability for a p

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H03K-017/22
  • H03L-007/00
출원번호 US-0825359 (1997-03-28)
발명자 / 주소
  • Graf
  • III W. Alfred
출원인 / 주소
  • Cypress Semiconductor Corp.
대리인 / 주소
    Blakely, Sokoloff, Taylory & Zafman LLP
인용정보 피인용 횟수 : 61  인용 특허 : 4

초록

A programmable device includes a circuit for generating an asynchronous logic derived clock signal from one or more of a number of input signals. Circuits for synchronizing the asynchronous logic derived clock signal to a reference clock signal are coupled to the circuit for generating. The circuits

대표청구항

[ What is claimed is:] [1.] A circuit, comprising:means for generating an asynchronous logic derived clock signal as a logical combination of a plurality of input signals using one or more logic gates; andmeans for synchronizing said asynchronous logic derived clock signal to a reference clock signa

이 특허에 인용된 특허 (4)

  1. Goto Akio (Hachioji JA) Okamoto Shigenori (Tama JA) Asakawa Shigeru (Fujisawa JA) Sugiyama Fumio (Yokohama JA), Bit synchronization circuit.
  2. Ludwig Thomas E. (Irvine CA), Circuit for synchronizing an asynchronous input signal to a high frequency clock.
  3. Offord Glen E. (Macungie PA), Low-power area-efficient and robust asynchronous-to-synchronous interface.
  4. Cheng Michael B. ; Wong Anthony Yap ; Hsiao Charles ; Wong Belle, Meta-stable-resistant front-end to a synchronizer with asynchronous clear and asynchronous second-stage clock selector.

이 특허를 인용한 특허 (61)

  1. Ramchandran, Amit, Adaptable datapath for a digital processing system.
  2. Ramchandran, Amit, Adaptable datapath for a digital processing system.
  3. Ramchandran, Amit, Adaptable datapath for a digital processing system.
  4. Ramchandran, Amit, Adaptable datapath for a digital processing system.
  5. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J., Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  6. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J., Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  7. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  8. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogenous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  9. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive processor for performing an operation with simple and complex units each comprising configurably interconnected heterogeneous elements.
  10. Master, Paul L.; Uvacek, Bohumir, Apparatus and method for adaptive multimedia reception and transmission in communication environments.
  11. Dike,Charles E.; Hawkins,David J., Apparatus and method for reducing power consumption by a data synchronizer.
  12. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
  13. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
  14. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
  15. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having fixed, application specific computational elements.
  16. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements.
  17. Heidari, Ghobad; Chang, Kuor Hsin; Master, Paul L.; Hogenauer, Eugene B.; Scheuermann, Walter James, Communications module, device, and method for implementing a system acquisition function.
  18. Master, Paul L.; Watson, John, Configurable hardware based digital imaging apparatus.
  19. Van Ess, David; Prendergast, Patrick N., Control circuit for optical transducers.
  20. Scheuermann, W. James; Hogenauer, Eugene B., Control node for multi-core system.
  21. Sunkavalli, Ravi; Verma, Hare K.; Gunwani, Manoj; Delaye, Elliott, Dedicated logic cells employing configurable logic and dedicated logic functions.
  22. Verma,Hare K.; Sunkavalli,Ravi; Gunwani,Manoj; Mulpuri,Chandra, Dedicated logic cells employing sequential logic and control logic functions.
  23. Gonion Jeffry E. ; Bilbrey Brett C., Digital signal processor using a reconfigurable array of macrocells.
  24. Furtek, Frederick Curtis; Master, Paul L., External memory controller.
  25. Furtek, Frederick Curtis; Master, Paul L., External memory controller node.
  26. Furtek, Fredrick Curtis; Master, Paul L., External memory controller node.
  27. Furtek, Fredrick Curtis; Master, Paul L., External memory controller node.
  28. Scheuermann,Walter James, Hardware implementation of the secure hash standard.
  29. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
  30. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
  31. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
  32. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
  33. Fibranz, Heiko; Plaettner, Eckehard, Integrated circuit having a synchronous and an asynchronous circuit and method for operating such an integrated circuit.
  34. Manohararajah, Valavan; Chromczak, Jeffrey Christopher; Lewis, David, Integrated circuits with improved register circuitry.
  35. Sambhwani, Sharad; Heidari, Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.
  36. Sambhwani, Sharad; Heidari, Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.
  37. Sambhwani,Sharad; Heidari,Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.
  38. Prendergast, Patrick N.; Kropf, Benjamin T., Method and apparatus for networked illumination devices.
  39. Campardo Giovanni,ITX ; Micheloni Rino,ITX ; Zammattio Matteo,ITX ; Ferrario Donato,ITX, Method and circuit for regulating the length of an ATD pulse signal.
  40. Larsen, Troy; Culley, Martin, Method and circuitry for switching from a synchronous mode of operation to an asynchronous mode of operation without any loss of data.
  41. Master, Paul L., Method and system for achieving individualized protected space in an operating system.
  42. Master, Paul L., Method and system for creating and programming an adaptive computing engine.
  43. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
  44. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
  45. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
  46. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
  47. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  48. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  49. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  50. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  51. Master,Paul L.; Hogenauer,Eugene; Wu,Bicheng William; Chuang,Dan MingLun; Freeman Benson,Bjorn, Method, system and program for developing and scheduling adaptive integrated circuity and corresponding control or configuration information.
  52. Master, Paul L., Profiling of software and circuit designs utilizing data operation analyses.
  53. Soriano, David; Molinet, Pep-Lluis; Rius, Marti, Serial bus system.
  54. Ess, David Van, Stochastic pulse generator device and method of same.
  55. Ess, David Van; Prendergast, Patrick N., Stochastic signal density modulation for optical transducer control.
  56. Van Ess, David; Prendergast, Patrick, Stochastic signal density modulation for optical transducer control.
  57. Van Ess, David; Prendergast, Patrick N, Stochastic signal density modulation for optical transducer control.
  58. Master,Paul L.; Watson,John, Storage and delivery of device features.
  59. Master, Paul L.; Watson, John, System for adapting device standards after manufacture.
  60. Master, Paul L.; Watson, John, System for authorizing functionality in adaptable hardware devices.
  61. Katragadda, Ramana; Spoltore, Paul; Howard, Ric, Task definition for specifying resource requirements.
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