|국가/구분||United States(US) Patent 등록|
|미국특허분류(USC)||307/131 ; 360/093 ; 340/650|
|발명자 / 주소|
|출원인 / 주소|
|대리인 / 주소||
|인용정보||피인용 횟수 : 15 인용 특허 : 5|
A circuit arrangement protects an FET power switch against damage from short circuits that may occur in the load connected between the drain terminal and an operating voltage source of the FET. The protection is achieved by the cooperation between a shunt resistor (3) connected between ground and the source terminal (S) of the FET and a gate voltage limiter (7) connected to the gate terminal of the FET. This cooperation limits the short circuit current through the FET until a short circuit detector (DT) provides a control signal that switches the FET off...
[ I claim:] [1.] A circuit arrangement for protecting against an overload an FET power switch (1) having a drain terminal (D), a source terminal (S), and a gate terminal (G), comprising a load (5) connected to said drain terminal (D) and to an operating voltage source (U.sub.B), a short circuit detector (DT) having an input connected to said source terminal (S), a microcontroller (9A) for controlling said FET power switch (1), said short circuit detector (DT) having an output (INT) connected to a control input of said microcontroller (9A) for supplying a...