초록 ▼

A circuit arrangement protects an FET power switch against damage from short circuits that may occur in the load connected between the drain terminal and an operating voltage source of the FET. The protection is achieved by the cooperation between a shunt resistor (3) connected between ground and th

A circuit arrangement protects an FET power switch against damage from short circuits that may occur in the load connected between the drain terminal and an operating voltage source of the FET. The protection is achieved by the cooperation between a shunt resistor (3) connected between ground and the source terminal (S) of the FET and a gate voltage limiter (7) connected to the gate terminal of the FET. This cooperation limits the short circuit current through the FET until a short circuit detector (DT) provides a control signal that switches the FET off.

대표청구항 ▼

[ I claim:] [1.] A circuit arrangement for protecting against an overload an FET power switch (1) having a drain terminal (D), a source terminal (S), and a gate terminal (G), comprising a load (5) connected to said drain terminal (D) and to an operating voltage source (U.sub.B), a short circuit dete

[ I claim:] [1.] A circuit arrangement for protecting against an overload an FET power switch (1) having a drain terminal (D), a source terminal (S), and a gate terminal (G), comprising a load (5) connected to said drain terminal (D) and to an operating voltage source (U.sub.B), a short circuit detector (DT) having an input connected to said source terminal (S), a microcontroller (9A) for controlling said FET power switch (1), said short circuit detector (DT) having an output (INT) connected to a control input of said microcontroller (9A) for supplying a control signal representing a short circuit to said control input of said microcontroller, a series resistor (9) connecting a control output of said microcontroller to said gate terminal (G), a gate terminal voltage limiter diode (7) connected to said gate terminal (G) and to a constant clamping voltage, and a shunt resistor (3) connected between said source terminal and ground for cooperation with said gate terminal voltage limiter diode (7) in limiting a short circuit current flowing through said FET power switch at least until said FET power switch (1) is switched off by said control signal in response to a short circuit.