초록 ▼

An automated, portable, and time conservative memory test system for identifying test parameters including type, control line configuration, depth, width, access time, and burst features of any one of a wide variety of synchronous memories including SDRAMs and SGRAMs, and whether an IC chip, bank, b

An automated, portable, and time conservative memory test system for identifying test parameters including type, control line configuration, depth, width, access time, and burst features of any one of a wide variety of synchronous memories including SDRAMs and SGRAMs, and whether an IC chip, bank, board or module, without requiring hardware modifications or additions to the memory device being identified, and without requiring storage of test patterns or characterizing data in the memory device.

대표청구항 ▼

[ What is claimed is:] [1.] A portable synchronous memory test system for testing of any one of a plurality of synchronous memories of differing types, control line configurations, width, depth, and access times, which comprises:test fixture means for receiving a synchronous memory;clock means for i

[ What is claimed is:] [1.] A portable synchronous memory test system for testing of any one of a plurality of synchronous memories of differing types, control line configurations, width, depth, and access times, which comprises:test fixture means for receiving a synchronous memory;clock means for issuing a clock signal to synchronize operation of said synchronous memory test system;a CPU in electrical communication with said clock means and receiving said clock signal for executing software program instructions;a ROM means in electrical communication with said CPU, and having stored therein a user interface program, an auto-ID program of nested loops for identifying said types, said control line configurations, said width, and said depth, test parameter tables of ordered entries of bit patterns representative of said plurality of synchronous memories and accessible by said auto-ID program, and test software programs for verifying parameters identified by said auto-ID program, each of said user interface program, said auto-ID program, and said test software programs having program instructions for execution by said CPU in identifying said synchronous memory;a RAM in electrical communication with said ROM means and said CPU, and having stored therein variable parameters for use during operation of said test software programs;refresh timer means in electrical communication with said CPU, said ROM and said RAM for interrupting said CPU to preserve memory contents of said test fixture means;oscillator means in electrical communication with said refresh timer means for timing a refresh cycle;a programmable delay line in electrical communication with said refresh timer means, said CPU, said RAM, and said ROM for generating data latch strobes for reading data from said test fixture means;data latch means in electrical communication with said program delay line, said refresh timer means, said CPU, said ROM, and said RAM for transferring data between said test fixture means and said synchronous memory test system in response to said data latch strobes;memory test controller means in electrical communication with said data latch means, said CPU, said programmable delay line said refresh timer means, said ROM and said RAM for generating control signals to be supplied to said test fixture means for automated identification of said synchronous memory; andcontrolled power supply means in electrical communication with said test fixture means, said memory test controller means, said data latch means, said CPU, said refresh timer means, said ROM, and said RAM for energizing said test fixture means.