초록 ▼

An CMOS interconnection method that permits small source/drain surface areas has been provided. The interconnection is applicable to both strap and via type connections. The surface areas of the small source/drain regions are extended into neighboring field oxide regions by forming a silicide film f

An CMOS interconnection method that permits small source/drain surface areas has been provided. The interconnection is applicable to both strap and via type connections. The surface areas of the small source/drain regions are extended into neighboring field oxide regions by forming a silicide film from the source/drain regions to the field oxide. Interconnections on the same metal level, or to another metal level are made by contact to the silicide covered field oxide. The source/drain regions need only be large enough to accept the silicide film. Transistors with small source/drain regions have smaller drain leakage currents and less parasitic capacitance. A CMOS transistor interconnection apparatus has also been provided.

대표청구항 ▼

[ What is claimed is:] [1.] A method for forming interconnections from at least a first transistor with source/drain regions, through surrounding field oxide regions, using gate electrode second sidewall structures, the method comprises the steps of:a) forming a gate electrode, with an underlying ga

[ What is claimed is:] [1.] A method for forming interconnections from at least a first transistor with source/drain regions, through surrounding field oxide regions, using gate electrode second sidewall structures, the method comprises the steps of:a) forming a gate electrode, with an underlying gate oxide layer and first oxide sidewalls, overlying portions of the source/drain regions;b) depositing a semiconductor film overlying the transistor, including the source/drain regions, the gate electrode, the first oxide sidewalls, and the surrounding field oxide regions;c) depositing a layer of insulator overlying the first semiconductor film;d) anisotropically etching the insulator deposited in Step c) to remove the insulator on the source/drain regions, gate electrode, and surrounding field oxide region, but not from the gate electrode sidewalls, whereby second sidewalls are formed;e) depositing a refractory metal layer overlying the semiconductor film, covering the source/drain regions and selected adjoining areas of field oxide; andf) annealing the semiconductor film deposited in Step b) and the refractory metal deposited in Step e) to form a silicide film overlying the source/drain regions and the selected adjoining areas of field oxide, whereby an electrical interconnection is made to the source/drain regions from the surrounding field oxide region to minimize the size of the source/drain regions.