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특허 상세정보

MyON담기
내보내기 페이스북 공유 카카오톡 공유

Method for manufacturing a CMOS self-aligned strapped interconnection

특허상세정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판) H01L-021/4763   
미국특허분류(USC) 438/618 ; 438/647 ; 438/655
출원번호 US-0090802 (1998-06-04)
발명자 / 주소
출원인 / 주소
대리인 / 주소
    Maliszewski
인용정보 피인용 횟수 : 107  인용 특허 : 11
초록
▼

An CMOS interconnection method that permits small source/drain surface areas has been provided. The interconnection is applicable to both strap and via type connections. The surface areas of the small source/drain regions are extended into neighboring field oxide regions by forming a silicide film from the source/drain regions to the field oxide. Interconnections on the same metal level, or to another metal level are made by contact to the silicide covered field oxide. The source/drain regions need only be large enough to accept the silicide film. Transi...

대표
청구항
▼

[ What is claimed is:] [1.] A method for forming interconnections from at least a first transistor with source/drain regions, through surrounding field oxide regions, using gate electrode second sidewall structures, the method comprises the steps of:a) forming a gate electrode, with an underlying gate oxide layer and first oxide sidewalls, overlying portions of the source/drain regions;b) depositing a semiconductor film overlying the transistor, including the source/drain regions, the gate electrode, the first oxide sidewalls, and the surrounding field o...

이 특허에 인용된 특허 (11)

  1. Stall Richard A. (Berkeley Heights NJ). Growth of oxide thin films using solid oxygen sources. USP1986064592927.
  2. Moslehi Mehrdad M. (Dallas TX). Local interconnect method and structure. USP1992105156994.
  3. Hwang Jeong-Mo (Plano TX). Local thinning of channel region for ultra-thin film SOI MOSFET with elevated source/drain. USP1996105567966.
  4. Sato Fumihiko (Tokyo JPX). Method for fabricating a vertical bipolar transistor with reduced parasitic capacitance between base and collector regio. USP1995075432104.
  5. Somekh Sasson (Los Altos Hills CA) Nulman Jaim (Palo Alto CA) Chang Mei (Cupertino CA). Method for forming low resistance and low defect density tungsten contacts to silicon semiconductor wafer. USP1993105250467.
  6. Ishihara Hiroyasu (Tokyo JPX). Method for manufacturing a thin-film transistor operable at high voltage. USP1991085039622.
  7. Hayashi Hiromi (Kawasaki JPX) Fushida Atsuo (Kawasaki JPX) Izawa Tetsuo (Kawasaki JPX) Katsube Masaki (Kawasaki JPX) Yamazaki Tatsuya (Kawasaki JPX). Method of making a semiconductor device having a silicide local interconnect. USP1997065635426.
  8. Peek Hermanus L. (Eindhoven NLX). Method of manufacturing semiconductor device. USP1989104877754.
  9. Brady Frederick T. (Chantilly VA) Haddad Nadim F. (Oakton VA) Edenfeld Arthur (Middlebrook VA). Method to prevent latch-up and improve breakdown volatge in SOI mosfets. USP1996065527724.
  10. Ozturk Mehmet C. (Cary NC) Grider Douglas T. (Raleigh NC) Sanganeria Mahesh K. (Raleigh NC) Ashburn Stanton P. (Cary NC). Selective deposition of doped silion-germanium alloy on semiconductor substrate. USP1993095242847.
  11. Ayukawa Akitsu (Nara JPX) Onishi Shigeo (Nara JPX). Semiconductor device. USP1993025183770.

이 특허를 인용한 특허 피인용횟수: 107

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  2. Becker, Scott T.. Cell circuit and layout with linear finfet structures. USP2017029563733.
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  7. Smayling, Michael C.; Becker, Scott T.. Coarse grid design methods and structures. USP2018039917056.
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  9. Smayling, Michael C.; Becker, Scott T.. Coarse grid design methods and structures. USP2014028658542.
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