초록 ▼

A memory controller design includes at least one memory instruction decoder de-embedded from a memory instruction processor wherein the memory instruction processor receives operations and logical address information from a host processor. The memory instruction processor converts the operations int

A memory controller design includes at least one memory instruction decoder de-embedded from a memory instruction processor wherein the memory instruction processor receives operations and logical address information from a host processor. The memory instruction processor converts the operations into generic memory instructions and translates the logical addresses into physical addresses. The memory instruction decoder further converts the generic memory instructions into memory specific control signals and converts the physical addresses into actual memory specific addresses. This design permits the memory instruction processor to be designed and finalized before an actual memory type is selected for system use at which time the less complex memory instruction decoder can be designed.

대표청구항 ▼

[ What is claimed is:] [18.] A method, in a cache memory controller, for interfacing a cache memory to a host processor such that data bandwidth is increased therebetween, said cache memory having a first and second memory type, said first memory type characterized by a first memory technology and s

[ What is claimed is:] [18.] A method, in a cache memory controller, for interfacing a cache memory to a host processor such that data bandwidth is increased therebetween, said cache memory having a first and second memory type, said first memory type characterized by a first memory technology and said second memory type characterized by a second memory technology different from the first memory technology, said cache memory controller coupled between said host processor and said cache memory, said method comprising steps of:(a) receiving host commands and logical addresses from said host processor in a memory instruction processor;(b) said memory instruction processor converting said host commands into generic memory instructions and said logical addresses into memory system addresses, said memory system addresses corresponding to one of said memory types;(c) translating said memory system addresses into physical addresses of said first memory type using a first memory instruction decoder, said first memory instruction decoder de-embedded from said memory instruction processor, said first memory instruction decoder also converting said generic memory instructions into control signals specific to said first memory technology; and(d) translating said memory system addresses into physical addresses of said second memory type using a second memory instruction decoder, said second memory instruction decoder de-embedded from said memory instruction processor, said second memory instruction decoder also converting said generic memory instructions into control signals specific to said second memory technology.