초록 ▼

A transport stream decoder/demultiplexer is provided which includes a program clock recovery circuit for recovering a program clock from program clock reference (PCR) values contained in selected transport packets. A processor is provided for extracting elementary stream data from transport packets

A transport stream decoder/demultiplexer is provided which includes a program clock recovery circuit for recovering a program clock from program clock reference (PCR) values contained in selected transport packets. A processor is provided for extracting elementary stream data from transport packets labeled with packet identification codes (PIDs) that are specified by a host processor. The processor separately stores the elementary stream data of each stream. A host processor interface is also provided for transferring data between an external host processor and the program clock recovery circuit. A memory manager may be provided for storing the data extracted by the processor for each elementary stream in a corresponding queue. The queues may be maintained by the memory manager in an external RAM. A descrambler interface may be provided for transferring scrambled data and data derived from conditional access information between the processor and an external descrambler. In addition, at least one elementary stream interface, such as a video interface or audio interface, may be provided for outputting extracted elementary stream data for a particular elementary stream from a corresponding queue. Furthermore, a high speed interface may be provided for outputting transport packet data prior to data extraction by the processor.

대표청구항 ▼

[ The invention claimed is:] [1.] A transport stream demultiplexer for demultiplexing program data from transport packets, each of said transport packets having a packet identifier PID, a unique PID being assigned to packets carrying program clock references PCRs of a desired program, said apparatus

[ The invention claimed is:] [1.] A transport stream demultiplexer for demultiplexing program data from transport packets, each of said transport packets having a packet identifier PID, a unique PID being assigned to packets carrying program clock references PCRs of a desired program, said apparatus comprising:a first processor for extracting said unique PID assigned to transport packets carrying said PCRs of said desired program,a PCR circuit responsive to said unique PID, for extracting each PCR from each received transport packet having said unique PID,a PCR counter for producing a PCR clock count in response to a clock signal received at a clock input,an external host processor interface, for transferring to a second external processor one or more values on which a difference between a PCR clock count from said PCR counter and an extracted PCR from said PCR circuit depends and for receiving from the second external processor a digitally filtered PCR clock phase error based on said difference between said PCR clock count and said extracted PCR, anda digital to analog converter for converting said digitally filtered PCR clock phase error to analog form, and feeding said analog form of said digitally filtered PCR clock phase error via at least a voltage controlled oscillator VCXO to said clock input of said PCR counter, wherein an output of the VCXO is received at said clock input as said clock signal, so as to adjust a phase error of said PCR counter relative to said extracted PCR.