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Bond pad structure for the via plug process 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/522
출원번호 US-0929953 (1997-09-15)
발명자 / 주소
  • Shiue Ruey-Yun,TWX
  • Wu Wen-Teng,TWX
  • Shieh Pi-Chen,TWX
  • Liu Chin-Kai,TWX
출원인 / 주소
  • Taiwan Semiconductor Manufacturing Company, Ltd., TWX
대리인 / 주소
    Saile
인용정보 피인용 횟수 : 60  인용 특허 : 10

초록

A bond pad structure and method of forming the bond pad structure which provides for reliable interconnections between the bond pad structure and the next level of circuit integration. The bond pad structure uses three metal pads separated by layers of dielectric. Via plugs are formed between the fi

대표청구항

[ What is claimed is:] [1.] A bond pad structure, comprising:a first dielectric layer;a square first metal pad formed on said first dielectric layer;a second dielectric layer formed over said first metal pad;a square second metal pad formed over said second dielectric layer wherein said second metal

이 특허에 인용된 특허 (10)

  1. Heim Dorothy A. (San Jose CA), Composite bond pads for semiconductor devices.
  2. Alter Martin J. (Los Altos CA) Brown ; Jr. Clyde M. (Cupertino CA) Compton James B. (Los Gatos CA), Method for forming shorting contact for semiconductor which allows for relaxed alignment tolerance.
  3. Freeman ; Jr. John L. (Mesa AZ) Tracy Clarence J. (Tempe AZ), Method for making a planar multi-layer metal bonding pad.
  4. Bryant Frank R. (Denton TX) Chen Fusen E. (Milpitas CA), Semiconductor bond pad structure and method.
  5. Fujiki Noriaki,JPX ; Yamashita Takashi,JPX, Semiconductor device and bonding pad structure therefor.
  6. Sato Hisakatsu,JPX, Semiconductor device having a multi-latered wiring structure.
  7. Nakamura Makiko (Tokyo JPX) Fukuda Yasuhiro (Tokyo JPX) Tatara Yasuyuki (Tokyo JPX) Harada Yusuke (Tokyo JPX) Onoda Hiroshi (Tokyo JPX), Semiconductor device having a multi-layered conductive structure which includes an aluminum alloy layer, a high melting.
  8. Kikkawa Takamaro (Tokyo JPX), Semiconductor device having multi-layer electrode wiring.
  9. Nozaki Masahiko (Hyogo JPX), Semiconductor device structure including multiple interconnection layers with interlayer insulating films.
  10. DiGiacomo Giulio (Hopewell Junction NY) Cammarano Armando S. (Hyde Park NY) DiPaolo Nunzio (Poughkeepsie NY), Structure and method for corrosion and stress-resistant interconnecting metallurgy.

이 특허를 인용한 특허 (60)

  1. Huang, Tai-Chun; Yao, Chih-Hsiang; Hsieh, Ching-Hua, Bond pad for flip chip package.
  2. Su,Wen Tsai; Shen,Chin Chi; Chiu,Ming Jer; Chen,Chih Chiang, Bond pad structure.
  3. Chen-Wen Tsai TW; Chung-Ju Wu TW; Wei-Feng Lin TW, Bond pad structure and its method of fabricating.
  4. Tsai, Chen-Wen; Wu, Chung-Ju; Lin, Wei-Feng, Bond pad structure and its method of fabricating.
  5. Brett H. Engel ; Vincent James McGahay ; Henry Atkinson Nye, III, Bond pad structure and method for reduced downward force wirebonding.
  6. Hsia, Chin Chiu; Yao, Chih Hsiang; Huang, Tai Chun; Peng, Chih Tang, Bond pad structure for wire bonding.
  7. Chou, Kuo-Yu; Ong, Tong-Chern, Bond pads using mesh pattern via structures for protecting devices/circuits under I/O pads.
  8. Edgar R. Zuniga ; Samuel A. Ciani, Bonding over integrated circuits.
  9. Huang Min-San,TWX ; Fu Huan-Sung,TWX ; Wang Ling-Sung,TWX ; Wang Yong-Kang,TWX ; Wu Jyh-Ren,TWX ; Yang Shung-Bing,TWX, Bonding pad structure.
  10. Cho,Tai Heui; Kang,Hyuck Jin; Kim,Min Chul; Kim,Byung Yoon, Bonding pad structure of a semiconductor device.
  11. Cho, Tai-Heui; Kang, Hyuck-Jin; Kim, Min-Chul; Kim, Byung-Yoon, Bonding pad structure of a semiconductor device and method for manufacturing the same.
  12. Yamaha Takahisa,JPX, Bonding pad structure of semiconductor device.
  13. Yu Chen Hua,TWX, Bonds pads equipped with heat dissipating rings and method for forming.
  14. Axel Christoph Brintzinger, Chip crack stop design for semiconductor chips.
  15. Skala Stephen L. ; Bothra Subhas ; Pramanik Dipu ; Shu William Kuang-Hua, Composite metallization structures for improved post bonding reliability.
  16. Yamamoto, Koji; Kumamoto, Nobuhisa; Matsumoto, Muneyuki, Damascene interconnection and semiconductor device.
  17. Yamamoto,Koji; Kumamoto,Nobuhisa; Matsumoto,Muneyuki, Damascene interconnection and semiconductor device.
  18. Shu, William Kuang-Hua, Die pad crack absorption system and method for integrated circuit chip fabrication.
  19. Chen, Hsien-Wei; Liu, Yu-Wen; Tsai, Hao-Yi; Jeng, Shin-Puu; Chen, Ying-Ju, Double solid metal pad with reduced area.
  20. Chen, Hsien-Wei; Liu, Yu-Wen; Tsai, Hao-Yi; Jeng, Shin-Puu; Chen, Ying-Ju, Double solid metal pad with reduced area.
  21. Kida Tsuyoshi,JPX ; Oyachi Kenji,JPX, Electrode structure of semiconductor element.
  22. Bothra Subhas ; Skala Stephen L. ; Pramanik Dipu, Electromigration impeding composite metallization lines and methods for making the same.
  23. Lin, Ying-Hsi, Integrated circuit device having pads structure formed thereon and method for forming the same.
  24. Lin, Ying-Hsi, Integrated circuit device having pads structure formed thereon and method for forming the same.
  25. Lin, Ying-Hsi, Integrated circuit device having pads structure formed thereon and method for forming the same.
  26. Vo, Nhat D.; Tran, Tu-Anh N.; Carpenter, Burton J.; Hong, Dae Y.; Miller, James W.; Phillips, Kendall D., Integrated circuit having pads and input/output (I/O) cells.
  27. Pozder,Scott K.; Hess,Kevin J.; Leung,Pak K.; Travis,Edward O.; Wilkerson,Brett P.; Wontor,David G.; Zhao,Jie Hua, Integrated circuit having structural support for a flip-chip interconnect pad and method therefor.
  28. Humphrey Guy H. ; Fisher Rory L. ; D'Amato Jerry, Integrated circuit having unique lead configuration.
  29. Kuo,Yian Liang; Lin,Yu Chang, Integrated circuit package bond pad having plurality of conductive members.
  30. Hess, Kevin J.; Downey, Susan H.; Miller, James W.; Yong, Cheng Choi, Method and apparatus for providing structural support for interconnect pad while allowing signal conductance.
  31. Hess,Kevin J.; Downey,Susan H.; Miller,James W.; Yong,Cheng Choi, Method and apparatus for providing structural support for interconnect pad while allowing signal conductance.
  32. Pozder,Scott K.; Kobayashi,Thomas S., Method for forming a bond pad interface.
  33. Pozder, Scott K.; Kobayashi, Thomas S., Method for forming a semiconductor device having a mechanically robust pad interface.
  34. Yamaha, Takahisa, Method for manufacturing a semiconductor device.
  35. Yamaha,Takahisa, Method of forming a bonding pad structure.
  36. Yamaha,Takahisa, Method of forming a bonding pad structure.
  37. Chen,Sheng Hsiung, Method of improving copper pad adhesion.
  38. Dias,Rajen; Chandran,Biju, Microelectronic device interconnects.
  39. Chen, Sheng-Hsiung; Chen, Shun Long; Lin, Hungtse, Modified pad for copper/low-k.
  40. Ho, Chung Hsiung; Hsiao, Wayne; Gan, Richard Te; Spehar, James Raymond, Multi-via redistribution layer for integrated circuits having solder balls.
  41. Mototsugu Okushima JP, Multilayer wiring structure and semiconductor device having the same, and manufacturing method therefor.
  42. Okushima Mototsugu,JPX, Multilayer wiring structure and semiconductor device having the same, and manufacturing method therefor.
  43. Lee, Tze-Liang; Huan, Yun-San, Pad structure to prompt excellent bondability for low-k intermetal dielectric layers.
  44. Lee, Tze-Liang; Huan, Yun-San, Pad structure to prompt excellent bondability for low-k intermetal dielectric layers.
  45. Chen, Yu-Kai; Hsu, Yeh-Chi, Pad structure, circuit carrier and integrated circuit chip.
  46. Tsao,Pei Haw; Huang,Chender; Hou,Shang Yu; Su,Chao Yuan; Hsu,Chia Hsiung, Semiconductor bond pad structures and methods of manufacturing thereof.
  47. Matsuoka,Yoshihiro; Imamura,Kazuyuki; Oshima,Masao; Suzuki,Takashi; Sawada,Toyoji, Semiconductor device.
  48. Kanaoka, Taku; Sahara, Masashi; Fukayama, Yoshio; Ebata, Yutaro; Higuchi, Kazuhisa; Fujishima, Koji, Semiconductor device and a method of manufacturing the same.
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  50. Kanaoka, Taku; Sahara, Masashi; Fukayama, Yoshio; Ebata, Yutaro; Higuchi, Kazuhisa; Fujishima, Koji, Semiconductor device and a method of manufacturing the same.
  51. Naoto Akiyama JP, Semiconductor device and method for manufacturing same.
  52. Mahler, Joachim; Haimerl, Alfred; Wieneke Kessler, Angela; Bauer, Michael, Semiconductor device including a stress buffer.
  53. Liang, Zhongning; Lous, Erik Jan, Semiconductor device with isolated intermetal dielectrics.
  54. Kanaoka, Taku; Sahara, Masashi; Fukayama, Yoshio; Ebata, Yutaro; Higuchi, Kazuhisa; Fujishima, Koji, Semiconductor device with pads overlapping wiring layers including dummy wiring.
  55. Kwon, Dong Whee; Lee, Jin Hyuk; Song, Yun Heub; Kang, Sa Yoon, Semiconductor devices with bonding pads having intermetal dielectric layer of hybrid configuration and methods of fabricating the same.
  56. Fan,Zhang; Chao,Zhang Bei; Wuping,Liu; Liep,Chok Kho; Choo,Hsia Liang; Kheng,Lim Yeow; Cuthbertson,Alan; Boon,Tan Juan, Structure and method for fabricating a bond pad structure.
  57. Fan,Zhang; Chao,Zhang Bei; Wuping,Liu; Liep,Chok Kho; Choo,Hsia Liang; Kheng,Lim Yeow; Cuthbertson,Alan; Boon,Tan Juan, Structure and method for fabricating a bond pad structure.
  58. Lu Chang-Ming,TWX ; Lu Shu-Ying,TWX, Structure of a bonding pad for semiconductor devices.
  59. Barth, Hans-Joachim; Pohl, Jens, Through substrate via semiconductor components.
  60. Ashton, Robert A.; Lytle, Steven A.; Roby, Mary D.; Thoma, Morgan J.; Vitkavage, Daniel J., Use of small openings in large topography features to improve dielectric thickness control and a method of manufacture thereof.
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