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Higher-speed parallel processing 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-015/80
출원번호 US-0978813 (1997-11-26)
우선권정보 JP-0297799 (1993-11-29)
발명자 / 주소
  • Date Atsushi,JPX
  • Hamaguchi Kazumasa,JPX
  • Kosugi Masato,JPX
  • Fukui Toshiyuki,JPX
출원인 / 주소
  • Canon Kabushiki Kaisha, JPX
대리인 / 주소
    Fitzpatrick, Cella, Harper & Scinto
인용정보 피인용 횟수 : 32  인용 특허 : 8

초록

An information processing apparatus which processes a large amount of data at high speed. The synchronizing signal has a cycle including a transfer period and a processing period. In the transfer period, data is transferred, e.g., from a data input unit to a first memory, and from the first memory t

대표청구항

[ What is claimed is:] [1.] An information processing apparatus comprising:storage means for storing data into a plurality of independent storage areas;processing means including a plurality of processors for respectively processing the data stored in the plurality of storage areas;connecting means

이 특허에 인용된 특허 (8)

  1. Hamaguchi Kazumasa (Kawasaki JPX), Block substitution method in a cache memory of a multiprocessor system.
  2. Eckart Glen A. (Salt Lake City UT), Computer graphics system with parallel processing using a switch structure.
  3. Yamazaki Isamu (Kawasaki JPX), Computer system with a configuration monitor.
  4. Bremner ; III David F. (Fort Collins CO), Distributed processing apparatus and method for use in global rendering.
  5. Imai Masaharu (Toyohashi JPX) Honsawa Kunio (Toyohashi JPX) Tomita Jota (Tokyo JPX), Filtering operation method for very high-speed image processing system.
  6. Littlefield Richard J. (Seattle WA), Parallel processor-based raster graphics system architecture.
  7. Balmer Keith (6 Salcombe Close Bedford (Bedfordshire) GB2 MK40 38A) Ing-Simmons Nicholas K. (74 Lincroft ; Oakley Bedford (Bedfordshire) TX GB2 MK43 7SS) Guttag Karl M. (4015 S. Sandy Ct. Missouri Ci, Switch matrix having integrated crosspoint logic and method of operation.
  8. Hattori Hiroshi (Kawasaki JPX), Three-dimensional computer graphic apparatus with designated processing order in pipeline processing.

이 특허를 인용한 특허 (32)

  1. Ishikawa, Hisashi, Apparatus and method for processing data.
  2. Ishikawa, Hisashi, Apparatus and method for processing data.
  3. Date,Atsushi; Kato,Katsunori; Yokoyama,Noboru; Maeda,Tadaaki; Fujiwara,Takafumi, Bus management based on bus status.
  4. Louzoun, Eliel; Ben-Shahar, Yifat, Communication between two embedded processors.
  5. Date, Atsushi, Controller of multi function device.
  6. Mehta,Kalpesh Dhanvantrai, Filter mechanism.
  7. Ushida, Katsutoshi; Naoi, Yuichi; Katahira, Yoshiaki; Morishita, Koichi, Image processing apparatus and image processing method.
  8. Ushida, Katsutoshi; Naoi, Yuichi; Katahira, Yoshiaki; Nakamura, Yasuyuki; Morishita, Koichi; Fukuo, Makoto, Image processing apparatus and image processing method.
  9. Ushida,Katsutoshi; Naoi,Yuichi; Katahira,Yoshiaki; Nakamura,Yasuyuki; Morishita,Koichi; Fukuo,Makoto, Image processing apparatus and image processing method.
  10. Tanaka, Junichi, Image processing device and image processing method.
  11. Lin,Tay Jyi; Hsiao,Pi Chen; Liu,Chih Wei; Jen,Chein Wei; Liao,I Tao; Huang,Po Han, Inter-cluster communication module using the memory access network.
  12. Susumu Naito JP; Toshiki Itoh JP, Matrix type liquid-crystal display with optical data communication feature.
  13. Atsushi Date JP; Katsunori Kato JP; Noboru Yokoyama JP; Tadaaki Maeda JP; Takafumi Fujiwara JP, Memory management for use with burst mode.
  14. Hamaguchi Kazumasa,JPX, Method and apparatus for cache coherency in an interconnecting network.
  15. Kagle,Jonathan C.; Odinak,Gilad, Method and apparatus for reducing image acquisition time in a digital imaging device.
  16. Kagle,Jonathan C.; Odinak,Gilad, Method and apparatus for reducing image acquisition time in a digital imaging device.
  17. Malek Robert Marion ; Gilbertson Roger L. ; Bauman Mitchell Anthony, Method of and apparatus for bandwidth control of transfers via a bi-directional interface.
  18. van der Wal Gooitzen Siemen ; Hansen Michael Wade ; Piacentino Michael Raymond ; Brehm Frederic William, Modular parallel-pipelined vision system for real-time video processing.
  19. Gonzalez, Nelson; Organvidez, Humberto, Motherboard for supporting multiple graphics cards.
  20. Gonzalez, Nelson; Organvidez, Humberto; Cabello, Ernesto; Organvidez, Juan H., Multiple parallel processor computer graphics system.
  21. Gonzalez,Nelson; Organvidez,Humberto; Cabello,Ernesto; Organvidez,Juan H., Multiple parallel processor computer graphics system.
  22. Rhee, Chae-Eun, On-chip bus architectures with interconnected switch points, semiconductor devices using the same and methods for communicating data in an on-chip bus architecture.
  23. Hayashi, Tsuneo, Pipeline processing system and information processing apparatus.
  24. Hayashi, Tsuneo, Pipeline processing system and information processing apparatus.
  25. Sporny, Manushantha (Manu); Butterfield, Robert Kenneth; James, Norton Kenneth; Gaffney, Patrick Quinn, Processing data using continuous processing task and binary routine.
  26. Mohamed Moataz A. ; Spence John R. ; Malich Kenneth W., Processor containing data path units with forwarding paths between two data path units and a unique configuration or register blocks.
  27. Shibata,Akira; Nakaya,Wataru, Surveillance system and image signal processing apparatus.
  28. Aggarwal, Gaurav; Khare, Rajendra, Tertiary content addressable memory based motion estimator.
  29. Ford, Jeff S.; Belote, Jeff, Video card with interchangeable connector module.
  30. Ford,Jeff S.; Belote,Jeff, Video card with interchangeable connector module.
  31. Ford,Jeff S.; Denton,Claude; Belote,Jeff; Stradley,David J., Workstation for processing and producing a video signal.
  32. Ford,Jeff S.; Denton,Claude; Belote,Jeff; Stradley,David J., Workstation for processing and producing a video signal.
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