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A non-intrusive power control for a fault tolerant computer system which uses redundant voting at the hardware clock level. The computer includes three or more commercial central processing units (CPUs) operating synchronously. Outputs to system memory and system bus are voted by a radiation toleran

A non-intrusive power control for a fault tolerant computer system which uses redundant voting at the hardware clock level. The computer includes three or more commercial central processing units (CPUs) operating synchronously. Outputs to system memory and system bus are voted by a radiation tolerant gate array which may be implemented in a custom integrated circuit. An interface control coupled to the voter can remove or connect power from a CPU and adjust CPU inputs, preventing damage to the components without terminating an operating program. The inputs and outputs at each write to and read from system memory are voted at each CPU clock cycle. A vote status and control circuit "reads" the status of the vote and controls the state of the CPUs using hardware and software. The system logic selects the best chance of recovering from a detected fault by re-synchronizing all CPUs, powering down a faulty CPU, or switching to a spare computer, resetting and re-booting the substituted CPU.

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[ What is claimed is:] [1.] A non-intrusive power control apparatus comprising:a plurality of central processing units (CPUs) (32) operating a running software application synchronously, each operating step of each of said plurality of CPUs (32) being accomplished in parallel and substantially simul

[ What is claimed is:] [1.] A non-intrusive power control apparatus comprising:a plurality of central processing units (CPUs) (32) operating a running software application synchronously, each operating step of each of said plurality of CPUs (32) being accomplished in parallel and substantially simultaneouslywith each of the other of said plurality of CPUs (32) each clock cycle of said CPUs (32), each one of said plurality of CPUs (32) having an input (33i) and an output (33o);a voter (34) having a voted output (35); said voter (34) coupled to each of said plurality of CPUs (32) and receiving said CPU output (33o); said voter (34) using redundant voting of said CPU output (33o) to detect a fault in any of said plurality of CPUs (32) whose output (33o) disagrees with CPU output (33o) of a majority of said plurality of CPUs (32); each said CPU output (33o) being compared one with another by said voter (34) each said clock cycle;a power bus (20) for furnishing a supply voltage (24) to each of said plurality of CPUs (32), said power bus (20) connected to each one of said plurality of CPUs (32); andsaid supply voltage (24) being removed from an affected CPU (32) and said CPU input (33i) being limited to non-stressed condition for said affected CPU (32) without terminating said running software application, when a potentially destructive fault is detected by said voter (34) in said affected CPU (32).