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Method of manufacturing ball grid arrays for improved testability 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/44
출원번호 US-0970184 (1997-11-14)
발명자 / 주소
  • Slocum Alexander H.
출원인 / 주소
  • Kinetrix, Inc.
대리인 / 주소
    Walsh
인용정보 피인용 횟수 : 20  인용 특허 : 10

초록 ▼

A ball grid array package for integrated circuit chips that is designed to facilitate testing. The balls are planarized with high precision to make electrical contact more accurate for testing. Contact, even on fine pitched arrays, can be readily made. A machine for planarizing the solder balls is d

대표청구항

[ What is claimed is:] [1.] A method of manufacturing integrated circuit chips comprising the steps of:a) forming an integrated circuit package having a plurality of solder balls on one surface thereof; andb) cutting, on each of the plurality of solder balls, a flat portion on a surface thereof.

이 특허에 인용된 특허 (10)

  1. Tago Masamoto (Tokyo JPX) Tanaka Kei (Tokyo JPX), Method and apparatus for forming bump structure used for flip-chip mounting, the bump structure and the flip-chip.
    상세보기
  2. Adamjee Waseem (Austin TX), Method for ball bumping a semiconductor device.
    상세보기
  3. Akram Salman (Boise ID) Farnworth Warren M. (Nampa ID) Wood Alan G. (Boise ID), Method for fabricating a self limiting silicon based interconnect for testing bare semiconductor dice.
    상세보기
  4. Koopman Nicholas G. (Raleigh NC) Rinne Glenn A. (Cary NC) Turlik Iwona (Raleigh NC) Yung Edward K. (Carrboro NC), Method for testing, burn-in, and/or programming of integrated circuit chips.
    상세보기
  5. Nakamura Yoshifumi (Neyagawa JPX) Bessho Yoshihiro (Higashiosaka JPX) Yuhaku Satoru (Osaka JPX) Hakotani Yasuhiko (Nishinomiya JPX) Itagaki Minehiro (Moriguchi JPX) Miura Kazuhiro (Osaka JPX), Method of manufacturing a ceramic substrate.
    상세보기
  6. Kim Il U. (Seoul KRX), Method of manufacturing a known good die array.
    상세보기
  7. Dunaway Thomas J. (St. Louis Park MN) Spielberger Richard K. (Maple Grove MN) Dicks Lori A. (New Hope MN) Loy Jerald M. (Anoka MN), Method of manufacturing a leadframe having conductive elements preformed with solder bumps.
    상세보기
  8. Tanioka Michinobu (Tokyo JPX) Suzuki Motoji (Tokyo JPX), Method of producing a flip chip.
    상세보기
  9. Kawakita Tetuo,JPX ; Hatada Kenzo,JPX, Process for bonding a semiconductor to a circuit substrate including a solder bump transferring step.
    상세보기
  10. Wood Alan G. (Boise ID) Doan Trung T. (Boise ID) Farnworth Warren M. (Nampa ID) Corbett Tim J. (Boise ID), Process for forming a raised portion on a projecting contact for electrical testing of a semiconductor.
    상세보기

이 특허를 인용한 특허 (20)

  1. Akram, Salman; Ahmad, Syed Sajid, Collar positionable about a periphery of a contact pad and around a conductive structure secured to the contact pads, semiconductor device components including same, and methods for fabricating same.
    상세보기
  2. Akram, Salman; Ahmad, Syed Sajid, Collar positionable about a periphery of a contact pad and around a conductive structure secured to the contact pads, semiconductor device components including same, and methods for fabricating same.
    상세보기
  3. Akram, Salman; Ahmad, Syed Sajid, Collar positionable about a periphery of a contact pad and around a conductive structure secured to the contact pads, semiconductor device components including same, and methods for fabricating same.
    상세보기
  4. Akram,Salman; Ahmad,Syed Sajid, Collar positionable about a periphery of a contact pad and around a conductive structure secured to the contact pads, semiconductor device components including same, and methods for fabricating same.
    상세보기
  5. Akram,Salman; Ahmad,Syed Sajid, Collars, support structures, and forms for protruding conductive structures.
    상세보기
  6. St. Amand, Roger D., Column and stacking balls package fabrication method and structure.
    상세보기
  7. Yen-Ming Chen TW; Kuo-Wei Lin TW; Cheng-Yu Chu TW; Fu-Jier Fan TW; Yang-Tung Fan TW; Chiou-Shian Peng TW; Shih-Jane Lin TW, Method for bumping and backlapping a semiconductor wafer.
    상세보기
  8. Mizukoshi, Masataka; Ishizuki, Yoshikatsu; Nakagawa, Kanae; Okamoto, Keishiro; Teshirogi, Kazuo; Sakai, Taiji, Method for forming bumps, semiconductor device and method for manufacturing same, substrate processing apparatus, and semiconductor manufacturing apparatus.
    상세보기
  9. Herren, Peter, Method for machining workpieces and machine tool.
    상세보기
  10. Dreiza, Mahmoud; Ballantine, Andrew; Shumway, Russell Scott, Molded cavity substrate MEMS package fabrication method and structure.
    상세보기
  11. Lange, Bernhard P; Coyle, Anthony L; Holloway, Jeffrey G, Non-pull back pad package with an additional solder standoff.
    상세보기
  12. Kim, Jin Seong; Park, Dong Joo; Kim, Kwang Ho; Ahn, Ye Sul, Semiconductor device and fabricating method thereof.
    상세보기
  13. Kim, Jin Seong; Park, Dong Joo; Kim, Kwang Ho; Yoo, Hee Yeoul; Jeong, Jeong Wung, Semiconductor device having overlapped via apertures.
    상세보기
  14. Kim, Jin Seong; Park, Dong Joo; Kim, Kwang Ho; Yoo, Hee Yeoul; Jeong, Jeong Wung, Semiconductor device having overlapped via apertures.
    상세보기
  15. Kim, Jin Seong; Park, Dong Joo; Kim, Kwang Ho; Yoo, Hee Yeoul; Jeong, Jeong Wung, Semiconductor device having overlapped via apertures.
    상세보기
  16. Darveaux, Robert Francis; St. Amand, Roger D.; Perelman, Vladimir, Stackable package and method.
    상세보기
  17. Darveaux, Robert Francis; St. Amand, Roger D.; Perelman, Vladimir, Stackable package and method.
    상세보기
  18. Bancod, Ludovico E.; Kim, Jin Seong; Wachtler, Kurt Peter, Stackable plasma cleaned via package and method.
    상세보기
  19. Darveaux, Robert Francis; Bancod, Ludovico; Yoshida, Akito, Stackable treated via package and method.
    상세보기
  20. St. Amand, Roger D., Underfill contacting stacking balls package fabrication method and structure.
    상세보기

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