$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

Separate set/reset paths for time critical signals 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H03K-005/12
출원번호 US-0885145 (1997-06-30)
발명자 / 주소
  • Proebsting Robert J.
출원인 / 주소
  • Townsend and Townsend and Crew LLP
대리인 / 주소
    Townsend and Townsend and Crew LLP
인용정보 피인용 횟수 : 41  인용 특허 : 9

초록

A digital system includes apparatus for propagating falling and rising edges of a digital signal through two separate data paths each optimized to maximize propagation of one edge of the signal. The first data path is structured to propagate the first transition (e.g., falling edge) of the digital s

대표청구항

[ What is claimed is:] [1.] Apparatus for propagating a digital signal of the type having first state transitions from a first digital state to a second digital state, and second state transitions the second digital state to the first digital state, the apparatus comprising:a first data path having

이 특허에 인용된 특허 (9)

  1. Ando Tsuyoshi (Tokyo JPX) Okano Yasunobu (Tokyo JPX), C-MOS logic circuit supplied with narrow width pulses converted from input pulses.
  2. Vinal Albert W. (Cary NC), Complementary logic input parallel (CLIP) logic circuit family.
  3. Proebsting Robert J. (27800 Edgerton Rd. Los Altos Hills CA 94022), Fast propagation technique in CMOS integrated circuits.
  4. Chan Tim W. (San Jose CA), High speed “OR”circuit configuration.
  5. Rogers Alan C. (South Portland ME), Monophase logic.
  6. Wendell Dennis L. (Pleasanton CA), Reset logic circuit and method.
  7. Redfield James W. (Pottstown PA), Self booting logical or circuit.
  8. Yamazaki Hirokazu (Kawasaki JPX) Yoshida Masanobu (Yokohama JPX), Semiconductor device for preventing malfunction caused by a noise.
  9. Proebsting Robert J. (Los Altos CA), Speed enhancement technique for CMOS circuits.

이 특허를 인용한 특허 (41)

  1. Pitkethly, Scott; Masleid, Robert Paul, Advanced repeater utilizing signal distribution delay.
  2. Pitkethly, Scott, Advanced repeater with duty cycle adjustment.
  3. Pitkethly, Scott, Advanced repeater with duty cycle adjustment.
  4. Pitkethly, Scott, Advanced repeater with duty cycle adjustment.
  5. Ferrant, Richard, Amplifier with a fan-out variable in time.
  6. Masleid, Robert Paul; Dholabhai, Vatsal, Circuit with enhanced mode and normal mode.
  7. Tsai, Sheng Yuan, Clock pin setting and clock driving circuit.
  8. Masleid, Robert P., Cold clock power reduction.
  9. Masleid,Robert P, Cold clock power reduction.
  10. Masleid,Robert P.; Giacomotto,Christophe, Complement reset buffer.
  11. Masleid, Robert P.; Harada, Akihiko; Giacomotto, Christophe, Complement reset multiplexer latch.
  12. Masleid, Robert Paul, Configurable delay chain with stacked inverter delay elements.
  13. Masleid, Robert Paul, Configurable delay chain with switching control for tail delay elements.
  14. Masleid, Robert Paul, Configurable tapered delay chain with multiple sizes of delay elements.
  15. Masleid, Robert P.; Pitkethly, Scott, Cross point switch.
  16. Masleid, Robert P.; Pitkethly, Scott, Cross point switch.
  17. Masleid, Robert P.; Pitkethly, Scott, Cross point switch.
  18. Brox,Martin; Kuzmenka,Maksim, Driver circuit with reduced jitter between circuit domains.
  19. Muraya,Keisuke, High-speed transmitter circuit.
  20. Masleid, Robert P, Inverting zipper repeater circuit.
  21. Masleid, Robert P., Inverting zipper repeater circuit.
  22. Masleid, Robert Paul, Inverting zipper repeater circuit.
  23. Masleid,Robert P., Inverting zipper repeater circuit.
  24. Masleid, Robert, Leakage efficient anti-glitch filter.
  25. Masleid, Robert P, Low latency clock distribution.
  26. Masleid, Robert Paul, Method and apparatus for process independent clock signal distribution.
  27. Kevin Dai ; Terry Chappell, Method and apparatus for ratioed logic structure that uses zero or negative threshold voltage.
  28. Ye Yibin ; Lu Shih-Lien ; De Vivek K. ; Narendra Siva, Method and apparatus for reducing signal transmission delay using skewed gates.
  29. Lu,Timothy, Method and apparatus to generate break before make signals for high speed TTL driver.
  30. Durham, Christopher McCall; Klim, Peter Juergen, Noise suppression circuit for suppressing above-ground noises.
  31. Masleid, Robert Paul, Power efficient multiplexer.
  32. Masleid, Robert Paul, Power efficient multiplexer.
  33. Masleid, Robert Paul, Power efficient multiplexer.
  34. Masleid, Robert Paul, Power efficient multiplexer.
  35. Geisler, Joseph Patrick; Dia, Kin Hooi, Pulse latches.
  36. Masleid, Robert Paul; Dholabhai, Vatsal; Klingner, Christian, Repeater circuit having different operating and reset voltage ranges, and methods thereof.
  37. Masleid, Robert Paul; Dholabhai, Vatsal, Repeater circuit with high performance repeater mode and normal repeater mode, wherein high performance repeater mode has fast reset capability.
  38. Kurokawa, Yoshiyuki, Semiconductor device and a display device.
  39. Kurokawa, Yoshiyuki, Semiconductor device and a display device.
  40. Kurokawa, Yoshiyuki, Semiconductor device and a display device.
  41. Masleid, Robert P.; Burr, James B., Stacked inverter delay chain.
섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로