초록

A circuit to implement a multi-channel parallel to serial conversion and a multi-channel serial to parallel conversion in one minimal RAM Matrix. The number of RAM cells (bits) needed is equivalent to the number of Flip-Flops used in a standard shift register and holding register implementation.

대표청구항 ▼

[ What is claimed is:] [1.] A selectable serial to parallel and parallel to serial converter circuit comprising:a first set of n registers each having an input, an output and a clock terminal, wherein said inputs are for receiving serial data streams;a second set of m registers each having an input,

[ What is claimed is:] [1.] A selectable serial to parallel and parallel to serial converter circuit comprising:a first set of n registers each having an input, an output and a clock terminal, wherein said inputs are for receiving serial data streams;a second set of m registers each having an input, an output, an enable and a clock terminal, wherein said inputs are for receiving parallel data streams;a RAM array having (n+m) inputs, connected to said outputs of said first set of n registers and said outputs of said second set of said m registers, and (n+m) outputs;a first MUX having n inputs, an output and a control terminal, wherein said n inputs of said first MUX are connected to n outputs of said RAM;a second MUX having m inputs, an output and a control terminal, wherein said m inputs of said second MUX are connected to m outputs of said RAM;a first shift register having m outputs, an input and a clock terminal, wherein said input of said first shift register is connected to said output of said second MUX and said clock terminal of said first shift register is connected to said clock terminals of said second set of m registers;a set of m hold registers each having an input, an output and a clock terminal, wherein said clock terminals of said m hold registers are connected to said clock terminals of said first set of n registers and each output of said first shift register is connected to one of said inputs of said m hold registers; anda second shift register having n outputs, an input and a clock terminal, wherein said clock terminal of said second shift register is connected to said clock terminal of said first shift register and said input of said second shift register is connected to said output of said first MUX, and further wherein said outputs of said second shift register provide parallel output data streams corresponding to said serial data streams received by said inputs of said first set of n registers and said outputs of said set of m hold registers provide serial output data streams corresponding to said parallel data streams received by said inputs of said second set of m registers.