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Defect gettering by induced stress 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-029/30
출원번호 US-0082892 (1998-05-21)
발명자 / 주소
  • Delgado Jose A.
  • McLachlan Craig J.
대리인 / 주소
    Jaeckle Fleischamann & Mugel, LLP
인용정보 피인용 횟수 : 53  인용 특허 : 12

초록

The present invention induces provides a gettering trench on the front surface of a device substrate. In one embodiment it induces stress and simultaneously forms a gettering zone 40 for gettering impurities in an integrated circuit structure. In another embodiment, the trench is filled with getteri

대표청구항

[ We claim the following:] [1.] An integrated circuit with a gettering site for gettering impurities comprising:a monocrystalline semiconductor device substrate having a front surface and an upper portion suitable for device formation, the upper portion of said semiconductor device substrate having

이 특허에 인용된 특허 (12)

  1. Hochberg Arthur K. (Torrance CA), Dielectrically isolated semiconductor devices.
  2. Bledsoe Jerry L. (Tucson AZ), Front-surface N+gettering techniques for reducing noise in integrated circuits.
  3. Hill Dale E. (Kirkwood MO), Gettering.
  4. Kohyama Yusuke (Yokosuka JPX), Gettering of unwanted metal impurity introduced into semiconductor substrate during trench formation.
  5. Edmonds Harold D. (Hopewell Junction NY) Markovits Gary (Poughkeepsie NY), High performance silicon wafer and fabrication process.
  6. Aronowitz Sheldon (San Jose CA) Hart Courtney L. (Los Gatos CA), Method for forming isolated semiconductor structures.
  7. Schwalke Udo (Heldenstein DEX), Method for producing an insulating trench in an SOI substrate.
  8. Chu Shao-Fu (Hopewell Junction NY) Ho Allen P. (Sunnyvale CA) Horng Cheng T. (San Jose CA) Kemlage Bernard M. (Kingston NY), Method of forming wide, deep dielectric filled isolation trenches in the surface of a silicon semiconductor substrate.
  9. Baba Yoshiro (Yokohama JPX) Koshino Yutaka (Yokohama JPX) Osawa Akihiko (Tokyo JPX) Yanagiya Satoshi (Kawasaki JPX), Method of making complete dielectric isolation structure in semiconductor integrated circuit.
  10. Tomita Hiroshi,JPX ; Takahashi Mami,JPX ; Yamabe Kikuo,JPX, Semiconductor device having an extrinsic gettering film.
  11. Morita Naoyuki (Nagano JPX), Semiconductor device with interlayer insulating film covering the chip scribe lines.
  12. Gaul Stephen J. (Melbourne FL) Hemmenway Donald F. (Melbourne FL), Trench isolation stress relief.

이 특허를 인용한 특허 (53)

  1. Lin, Mou-Shiung; Lee, Jin-Yuan, Chip packages having dual DMOS devices with power management integrated circuits.
  2. Lin,Mou Shiung, Chip structure with redistribution traces.
  3. Matthew S. Buynoski, Frontside SOI gettering with phosphorus doping.
  4. Lin, Mou-Shiung, High performance system-on-chip inductor using post passivation process.
  5. Lin, Mou-Shing, High performance system-on-chip using post passivation process.
  6. Lin, Mou-Shiung, High performance system-on-chip using post passivation process.
  7. Chan, Simon Siu-Sing, Inert atom implantation method for SOI gettering.
  8. Lee,Jin Yuan; Lin,Mou Shiung, Method for making high-performance RF integrated circuits.
  9. Lin, Mou-Shiung; Lee, Jin-Yuan, Method for making high-performance RF integrated circuits.
  10. Lin, Mou-Shiung; Lee, Jin-Yuan, Method for making high-performance RF integrated circuits.
  11. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Post passivation interconnection process and structures.
  12. Lin, Mou Shiung; Lee, Jin Yuan, Post passivation interconnection schemes on top of IC chip.
  13. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
  14. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
  15. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
  16. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
  17. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
  18. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
  19. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation interconnection schemes on top of IC chip.
  20. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation interconnection schemes on top of IC chip.
  21. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation interconnection schemes on top of IC chip.
  22. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation interconnection schemes on top of IC chip.
  23. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation interconnection schemes on top of IC chip.
  24. Lin, Mou Shiung; Lee, Jin Yuan, Post passivation interconnection schemes on top of IC chips.
  25. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chips.
  26. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation interconnection schemes on top of IC chips.
  27. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation interconnection schemes on top of IC chips.
  28. Lin, Mou-Shiung, Post passivation interconnection schemes on top of the IC chips.
  29. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Post passivation interconnection schemes on top of the IC chips.
  30. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Post passivation interconnection schemes on top of the IC chips.
  31. Lin,Mou Shiung, Post passivation interconnection schemes on top of the IC chips.
  32. Lin,Mou Shiung; Chou,Chiu Ming; Chou,Chien Kang, Post passivation interconnection schemes on top of the IC chips.
  33. Lin,Mou Shiung; Chou,Chiu Ming; Chou,Chien Kang, Post passivation interconnection schemes on top of the IC chips.
  34. Lin,Mou Shiung; Chou,Chiu Ming; Chou,Chien Kang, Post passivation interconnection schemes on top of the IC chips.
  35. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation interconnection schemes on top of the IC chips.
  36. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation interconnection schemes on top of the IC chips.
  37. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation interconnection schemes on top of the IC chips.
  38. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation interconnection schemes on top of the IC chips.
  39. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Post passivation interconnection structures.
  40. Montanini, Pietro; Ammendola, Giuseppe; Depetro, Riccardo; Mottura, Marta, SOI device with contact trenches formed during epitaxial growing.
  41. Witold P. Maszara, SOI semiconductor device opening implantation gettering method.
  42. Sato, Tsutomu; Mizushima, Ichiro; Tsunashima, Yoshitaka; Iinuma, Toshihiko; Miyano, Kiyotaka, Semiconductor device and method of manufacturing the same.
  43. Sato, Tsutomu; Mizushima, Ichiro; Tsunashima, Yoshitaka; Iinuma, Toshihiko; Miyano, Kiyotaka, Semiconductor device and method of manufacturing the same.
  44. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  45. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  46. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  47. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  48. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  49. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  50. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  51. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Top layers of metal for integrated circuits.
  52. Lin,Mou Shiung; Chou,Chiu Ming; Chou,Chien Kang, Top layers of metal for integrated circuits.
  53. Lin, Mou-Shiung; Wei, Gu-Yeon, Voltage regulator integrated with semiconductor chip.
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