초록 ▼

Disclosed are methods and apparatuses for use with a host computer system that optimize the timing and sizing of data blocks that are part of an ATM PDU that is to be transmitted over an ATM network. The data blocks are transferred from the host's memory to a local memory in a network interface circ

Disclosed are methods and apparatuses for use with a host computer system that optimize the timing and sizing of data blocks that are part of an ATM PDU that is to be transmitted over an ATM network. The data blocks are transferred from the host's memory to a local memory in a network interface circuit. The network interface circuit includes a memory access circuit, a segmenting circuit, a local memory, and a scheduling circuit. The memory access circuit accesses the host's memory and fetches an initial size block of a data packet therefrom and supplies the block of the data to the segmenting circuit which segments the block of the data into a plurality of linked cells. The plurality of linked cells are then stored in the local memory. The scheduling circuit retrieves the linked cells in a predetermined order and transmits each of them over a network connection at a specific time. When the remaining number of the stored plurality of linked cells falls below a defined level, the scheduling circuit requests that the memory access circuit fetch subsequent or burst size block of the data packet. This process continues until such time as all of the data packet has been transmitted over the network connection.

대표청구항 ▼

[ What is claimed is:] [1.] A network interface circuit for use with a computer system having a first memory capable of storing a data packet having a plurality of data payloads awaiting transmission over a network connection, said network interface circuit comprising:a memory access circuit capable

[ What is claimed is:] [1.] A network interface circuit for use with a computer system having a first memory capable of storing a data packet having a plurality of data payloads awaiting transmission over a network connection, said network interface circuit comprising:a memory access circuit capable of being coupled to said first memory and configured to access said first memory and fetch a block of said data packet from said first memory, such that said block is less than the data packet and more than a single one of the plurality of data payloads;a segmenting circuit coupled to said memory access circuit and configured to segment said block of said data packet received therefrom into a plurality of linked cells, and to output said plurality of linked cells;a second memory coupled to said segmenting circuit and configured to store said plurality of linked cells, the plurality of linked cells being arranged in a manner that is compatible with a transmission of data for multiple virtual circuits over the network connection; anda scheduling circuit coupled to said memory access circuit, said segmenting circuit, and said second memory circuit, and configured to retrieve each of said plurality of linked cells in a predetermined order from said second memory, and capable of being coupled to said network connection and configured to transmit each of said plurality of linked cells over said network connection, and to request that said memory access circuit fetch another said block of said data packet from said first memory when a remaining number of said plurality of linked cells stored in said second memory falls below a defined level until such time as all of said plurality of data payloads within said data packet have been transmitted over said network connection; rein the block is an initial block for initializing the scheduling circuit of the network interface circuit when it is a first block fetched and the block is a data burst programmed for a selected virtual circuit when it is other than the first block fetched.