초록 ▼

The details of an improved correlator and efficient method of correlation are disclosed. The last M received signal samples are compared with all shifts of a given M-bit binary codeword. The correlator adds or subtracts each of the signal samples accordingly, as the corresponding shift of the codewo

The details of an improved correlator and efficient method of correlation are disclosed. The last M received signal samples are compared with all shifts of a given M-bit binary codeword. The correlator adds or subtracts each of the signal samples accordingly, as the corresponding shift of the codeword contains a binary "1" or "0" in that position. The total is output for each new signal sample received, with a shift of one position between the signal samples and the codeword.

대표청구항 ▼

[ What is claimed is:] [24.] A correlator, comprising:a timing controller responsive to a clock signal;an input signal storage means for storing input signals;a latch coupled to an output of said input signal storage means, for sampling said input signals;a signal combining and selecting means coupl

[ What is claimed is:] [24.] A correlator, comprising:a timing controller responsive to a clock signal;an input signal storage means for storing input signals;a latch coupled to an output of said input signal storage means, for sampling said input signals;a signal combining and selecting means coupled to an output of said latch and said input signal storage means, for selecting sample combinations of said input signals;a mapping logic means coupled to an input of said signal combining and selecting means and to an output of said timing controller, for generating a sign pattern based on a bit pattern of a codeword being correlated with said input signals;a sign modifier coupled to an output of said mapping logic means, said signal combining and selecting means, and said timing controller;an address offset storage register coupled to said mapping logic means and said timing controller; andan output signal storage means coupled to said address offset storage means, said sign modifier, and said timing controller, for temporarily storing a correlated output signal.