초록 ▼

In a level shift circuit having a bias circuit and an output circuit, the current consumption of the bias circuit can be suppressed, and further the delay of the output signal relative to the input signal can be reduced. The ratio circuit comprises a bias circuit block (5) composed of a transistor (

In a level shift circuit having a bias circuit and an output circuit, the current consumption of the bias circuit can be suppressed, and further the delay of the output signal relative to the input signal can be reduced. The ratio circuit comprises a bias circuit block (5) composed of a transistor (1) connected to a high potential power source (7) and having a gate to which an input bias INBIAS is applied through a bias input terminal (11), a transistor (2) connected in series to the transistor (1) so as to function as a resistance, and a transistor (13) connected in series to the transistor (2) and a low potential power source (8); and an output circuit block (6) composed of a transistor (3) connected to the high potential power source (7) and having a gate to which an input signal IN is applied through an input terminal (10) and a drain from which an output signal OUT is derived to an output terminal (12), and a transistor (4) connected in series to the transistor (3) and a low potential power source (8). Further, a voltage VBIAS1 is applied from the drain of the transistor (1) to the gate of the transistor (4), and further a switching signal is applied from the drain of the transistor (3) to the gate of the transistor (13).

대표청구항 ▼

[ What is claimed is:] [1.] A semiconductor circuit, comprising:a first transistor with a first end thereof connected to a first power source and a gate of said first transistor being connected to a bias input terminal to which a constant voltage is applied;a second transistor connected to a second

[ What is claimed is:] [1.] A semiconductor circuit, comprising:a first transistor with a first end thereof connected to a first power source and a gate of said first transistor being connected to a bias input terminal to which a constant voltage is applied;a second transistor connected to a second end of said first transistor;a third transistor connected to said second transistor and a second power source;a fourth transistor with a first end connected to the first power source and a gate thereof connected to an input signal terminal; anda fifth transistor connected between a second end of said fourth transistor and the second power source and to a gate of the fifth transistor a bias voltage is applied from the second end of said first transistor;wherein a voltage is applied from the drain of the first transistor to the gate of the fifth transistor, a switching signal is applied from the drain of the fourth transistor to the gate of the third transistor, and an output terminal connected to a second end of said fourth transistor and to a gate of said third transistor outputs an output signal.