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Shared, reconfigurable memory architectures for digital signal processing

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-012/00
출원번호 US-0821326 (1997-03-21)
발명자 / 주소
  • Rubinstein Richard
인용정보 피인용 횟수 : 31  인용 특허 : 9

초록

Architectures and circuits are described for various implementations of a memory-centric computing system for DSP and other compute-intensive applications. A shared, reconfigurable memory system is accessible to both a host processor or controller and to one or more execution units such as a DSP exe

대표청구항

[ I claim:] [1.] A memory system for use in digital signal processing comprising:an array of memory cells;the array of memory cells including a plurality of word lines, each word line arranged for accessing a corresponding row of the memory cells;the array of memory cells further including a plurali

이 특허에 인용된 특허 (9)

  1. Bhatia Rohit (Vancouver WA) Furuta Masaru (Tenri JPX), Apparatus and method for preventing I/O bandwidth limitations in fast fourier transform processors.
  2. Yamaguchi Seiji (Osaka JPX), Cache memory for efficient access with address selectors.
  3. Yamazaki Takanaga (Kodaira JPX) Baba Shiro (Tokorozawa NJ JPX) Kurakazu Keiichi (Princeton NJ) Ando Masaharu (Kodaira JPX) Tanaka Toshio (Yokohama JPX) Kaneko Susumu (Mitaka JPX), Data processing system for development of outline fonts.
  4. Leary Kevin W. (Walpole MA) Donahue James D. (Waltham MA), Data processor apparatus and method with selective caching of instructions.
  5. Siegel Mark D. (Fort Worth TX), Dual buffer cache system for transferring audio compact disk subchannel information to a computer.
  6. Levy Hanoch (Rockville MD) Morris Robert J. T. (Los Gatos CA), Method for the assignment of request streams to cache memories.
  7. Sugibayashi Tadahiko (Tokyo JPX), Semiconductor memory device with improved indicator of state of redundant structure.
  8. Fadavi-Ardekani Jalil (Orefield PA), Signal processing system having reduced memory space.
  9. Dalton David C. (Tucson AZ) Cover Roger W. (Tucson AZ) Andelfinger Richard (Thornton CO), Variable-size first in first out memory with data manipulation capabilities.

이 특허를 인용한 특허 (31)

  1. Ramchandran, Amit, Adaptable datapath for a digital processing system.
  2. Ramchandran, Amit, Adaptable datapath for a digital processing system.
  3. Ramchandran, Amit, Adaptable datapath for a digital processing system.
  4. Ramchandran, Amit, Adaptable datapath for a digital processing system.
  5. Nguyen, Trung; Nguyen, Hang; Brooks, John W.; Gill, Parminder K., Control system, storage device and method for controlling access to a shared memory using a bus control or handshaking protocol.
  6. Bays, Laurence Edward; Fadavi-Ardekani, Jalil; Gutta, Srinivasa; Kermani, Bahram Ghaffarzadeh; Niescier, Richard Joseph; Smith, Geoffrey Lawrence; Soto, Walter G.; Greenwood, Daniel K., Dynamic partitioning of memory banks among multiple agents.
  7. Rao, Hari; Du, Yun; Yu, Chun, Dynamic power saving memory architecture.
  8. Herr,Brian D.; Kavaky,Joseph J., Dynamic self-tuning memory management method and system.
  9. Wong, Wanmo, Dynamic volume management for flash memories.
  10. Direnzo, Michael T.; Sella, Assaf; Goel, Manish; Lingam, Srinivas, Flexible and efficient memory utilization for high bandwidth receivers, integrated circuits, systems, methods and processes of manufacture.
  11. Ng, Bee Yee; Chan, Gaik Ming; Chromczak, Jeffrey Christopher; Schmit, Herman Henry, Lutram dummy read scheme during error detection and correction.
  12. Wong, Wanmo; Muthasamy, Karunakaran, Managing memory data recovery upon power loss.
  13. Wong, Wanmo; Muthusamy, Karunakaran, Managing memory data recovery upon power loss.
  14. Chang, Chih-Yu; Lu, Wei-Zheng; Jan, Fu-Chiang, Memory device and method operable to provide multi-port functionality thereof.
  15. Hertwig, Axel; Bauer, Harald; Fawer, Urs; Lippens, Paul, Memory sharing arrangement for an integrated multiprocessor system.
  16. Kawahito, Motohiro; Yasue, Toshiaki; Komatsu, Hideaki, Method and apparatus for eliminating redundant array range checks in a compiler.
  17. D'Errico Matthew J. ; Blumenau Steven M. ; Ofer Erez, Method and apparatus for managing the placement of data in a storage system to achieve increased system performance.
  18. Kawahito,Motohiro; Yasue,Toshiaki; Komatsu,Hideaki, Method using array range check information for generating versioning code before a loop for execution.
  19. Cathal G. Phelan ; Scott Harmel ; Rajesh Manapat ; Sunil Kumar Koduru, Method, architecture and circuitry for independently configuring a multiple array memory device.
  20. Wong,Wanmo; Muthusamy,Karunakaran, Multiple segment data object management.
  21. Kermani Bahram G., Non-preemptive memory locking mechanism in a shared resource system.
  22. Hartnett, Thomas D.; Kuslak, John S.; Longworth, Leroy J., Pipeline depth controller for an instruction processor.
  23. De Oliveira Kastrup Pereira,Bernardo, Processing method and apparatus for implementing systolic arrays.
  24. Tojima, Masayoshi; Miyajima, Hiroshi; Okajima, Yoshinori, Semiconductor integrated circuit device.
  25. Tojima,Masayoshi; Miyajima,Hiroshi; Okajima,Yoshinori, Semiconductor integrated circuit device.
  26. Wong, Wanmo; Muthusamy, Karunakaran, Single segment data object management.
  27. Sutardja, Sehat, System on chip with reconfigurable SRAM.
  28. Sutardja, Sehat, System on chip with reconfigurable SRAM.
  29. Sutardja, Sehat, System on chip with reconfigurable SRAM.
  30. Chang, Gary; Su, Hong-men, Time sharing a single port memory among a plurality of ports.
  31. Camer, Cristian; Komorowski, Marcin, Video multiviewer system using direct memory access (DMA) registers and block RAM.
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