초록 ▼

A single-ended match sense amplifier is provided for use in a translation lookaside buffer. The translation lookaside buffer includes a CAM array for storing x bit virtual addresses. The CAM array has n rows and x columns of CAM cells, each CAM cell having input node for receiving a virtual address

A single-ended match sense amplifier is provided for use in a translation lookaside buffer. The translation lookaside buffer includes a CAM array for storing x bit virtual addresses. The CAM array has n rows and x columns of CAM cells, each CAM cell having input node for receiving a virtual address bit signal, and a CAM miss/match node. N rows and minor sense amplifier circuits are coupled to n major sense amplifier circuits via n major sense lines. Each minor sense amplifier circuit has a minor sense input node, and a minor sense miss/match node. Each minor sense line is also coupled to at least two CAM cell miss/match nodes. A minor sense precharging device is coupled to each minor sense line. The minor sense precharging device selectively conducts current to precharge the minor sense lines to a first predetermined voltage. Each of the major sense amplifiers has a major sense input node, and a major sense miss/match node. Each major sense line is coupled to at least two minor sense miss/match nodes and one major sense input node. Major sense precharging devices are coupled to each major sense line. The major sense precharging devices selectively conduct current to precharge the major sense lines to the first predetermined voltage.

대표청구항 ▼

[ What is claimed is:] [1.] A translation lookaside buffer comprising:a cam array for storing x-bit virtual addresses, the cam array having n rows and x columns of cam cells, each cam cell having an input node for receiving a virtual address bit signal, and a cam miss/match node;n rows of minor sens

[ What is claimed is:] [1.] A translation lookaside buffer comprising:a cam array for storing x-bit virtual addresses, the cam array having n rows and x columns of cam cells, each cam cell having an input node for receiving a virtual address bit signal, and a cam miss/match node;n rows of minor sense amplifier circuits, each minor sense amplifier circuit having a minor sense input node, and a minor sense miss/match node;n rows of minor sense lines, each minor sense line being coupled to at least two cam cell miss/match nodes and to one minor sense input node;a minor sense precharging device coupled to each minor sense line, wherein the minor sense precharging devices selectively conduct current to precharge the minor sense lines to a first predetermined voltage;n major sense amplifier circuits, each major sense amplifier circuit having a major sense input node, and a major sense miss/match node;n major sense lines, each major sense line being coupled to at least two minor sense miss/match nodes of at least two minor sense amplifier circuits, respectively, and one major sense input node of a major sense amplifier circuit; anda major sense precharging device coupled to each major sense line, wherein the major sense precharging devices selectively conduct current to precharge the major sense lines to the first predetermined voltage.