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Stiffener with integrated heat sink attachment 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H05K-007/20
출원번호 US-0850076 (1997-05-02)
발명자 / 주소
  • Mertol Atila
출원인 / 주소
  • LSI Logic Corporation
인용정보 피인용 횟수 : 59  인용 특허 : 3

초록

An electronic semiconductor device package, the package comprising: a substrate having traces; a die attached to the substrate; first level interconnects of the die to the traces of the substrate; and a stiffener attached to the substrate, wherein the stiffener comprises at least one clip. A system

대표청구항

[ I claim:] [1.] An electronic semiconductor device package, said package comprising:a substrate having traces;a die attached to said substrate;first level interconnects electrically coupling said die to the traces of said substrate;a stiffener attached to said substrate, wherein said stiffener comp

이 특허에 인용된 특허 (3)

  1. Baker Don L. (Johnson City NY) Funari Joseph (Vestal NY) Otto William F. (Rochester MN) Sammakia Bahgat G. (Johnson City NY) Stutzman Randall J. (Vestal NY), Electronic assembly with enhanced heat sinking.
  2. Berndlmaier Erich (Wappingers Falls NY) Clark Bernard T. (Poughquag NY) Dorler Jack A. (Wappingers Falls NY), Heat transfer structure for integrated circuit package.
  3. Dawson ; deceased Peter F. (late of Portola Valley CA by Shirley B. Dawson ; executrix ) Leibovitz Jacques (San Jose CA) Nagesh Voddarahalli K. (Cupertino CA), Low cost, high thermal performance package for flip chips with low mechanical stress on chip.

이 특허를 인용한 특허 (59)

  1. Hung, Wensen; Huang, Szu-Po; Chen, Kim Hong; Jeng, Shin-Puu, 3DIC packages with heat dissipation structures.
  2. Searls, Damion T.; Dishongh, Terrance J.; Pullen, David, Apparatus and method for passive phase change thermal management.
  3. Searls, Damion T.; Dishongh, Terrance J.; Pullen, David, Apparatus and method for passive phase change thermal management.
  4. Sathe, Ajit V., Arrangements to provide mechanical stiffening elements to a thin-core or coreless substrate.
  5. Tao Su,TWX ; Wu Chin-Long,TWX ; Huang Tai-Chun,TWX ; Huang Han-Hsiang,TWX ; Chen Shih-Kuang,TWX ; Chao Shin-Hua,TWX, Ball grid array semiconductor package having improved heat dissipation efficiency, overall electrical performance and enhanced bonding capability.
  6. Duan, Guo-Hua; Li, Fu-Chun; Li, Yong; Lin, Yu-Shu; Peng, Shu-Sheng; Chen, Wen-Hsiung; Chen, Shin-Wen, Camera module.
  7. Hammond, Mark Stuart; Tormey, Ellen Schwartz; Thaler, Barry Jay; Hozer, Leszek; Chen, Hung-tse Daniel; Geller, Bernard Dov; Frederickson, Gerard, Ceramic multilayer circuit boards mounted on a patterned metal support substrate.
  8. Mueller-Hipper, Andreas; Pueschner, Frank, Chip module and method for producing a chip module.
  9. Hsu, Han Cheng; Yeh, Ting Chang, Chip package device and manufacturing method thereof.
  10. Bonthron, Andrew J.; Walworth, Darren Jay, Chip-scale semiconductor die packaging method.
  11. Bonthron, Andrew J.; Walworth, Darren Jay, Chip-scale semiconductor die packaging method.
  12. McConville, Paul J.; Lefevre, Jason M.; Moore, Steven R.; Herrmann, Douglas K., Cooling control system.
  13. Shigyo, Toshikazu; Odakura, Yasunori; Tanabe, Itaru, Electrohydraulic control module.
  14. Combs, Edward G.; Sheppard, Robert P.; Pun, Tai Wai; Ng, Hau Wan; Fan, Chun Ho; McLellen, Neil Robert, Enhanced thermal dissipation integrated circuit package.
  15. Patrizio Vinciarelli ; John R. Saxelby, Jr., Heat dissipation for electronic components.
  16. Kalyandurg, Satyan, Heat sink attachment.
  17. Kalyandurg,Satyan, Heat sink attachment.
  18. Jeter, Michael A; Taylor, Ralph S., High power electronic package with enhanced cooling characteristics.
  19. Feld Peter,DEX ; Kroeckel Horst,DEX ; Vester Markus,DEX, High-frequency power amplifier.
  20. Albert,Roland, Hydraulic motor vehicle gearbox control device with a plastic hydraulic distribution plate and conductors integrated therein.
  21. Chen, Chung-Hao; Tang, Min Keen; Weng, Li-Sheng, Integrated circuit package including floating package stiffener.
  22. Chi, HeeJo; Cho, NamJu; Shin, HanGil, Integrated circuit packaging system with stiffener and method of manufacture thereof.
  23. Khanna,Vijayeshwar Das; Kuczynski,Joseph; Sinha,Arvind Kumar; Sri Jayantha,Sri M., Method and apparatus for optimizing heat transfer with electronic components.
  24. Searls,Damion T.; Dishongh,Terrance J.; Pullen,David, Method for passive phase change thermal management.
  25. Hammond, Mark Stuart; Tormey, Ellen Schwartz; Thaler, Barry Jay; Hozer, Leszek; Chen, Hung-tse Daniel; Geller, Bernard Dov; Frederickson, Gerard, Method of making ceramic multilayer circuit boards mounted in a patterned metal support substrate.
  26. Combs,Edward G.; Sheppard,Robert P.; Pun,Tai Wai; Ng,Hau Wang; Fan,Chun Ho; McLellen,Neil Robert, Method of manufacturing an enhanced thermal dissipation integrated circuit package.
  27. Alcoe, David J.; Dalrymple, Thomas W.; Gaynes, Michael A.; Stutzman, Randall J., Module with adhesively attached heat sink.
  28. Sato Takeshi,JPX ; Sakaguchi Kenichi,JPX ; Tokunaga Hiromi,JPX, Package for semiconductor device having frame-like molded portion and producing method of the same.
  29. Shimizu Toshio,JPX ; Hiramoto Hiroyuki,JPX ; Sekiya Hiroki,JPX ; Kigima Kenji,JPX, Package for semiconductor power device and method for assembling the same.
  30. Shimizu, Toshio; Hiramoto, Hiroyuki; Sekiya, Hiroki; Kigima, Kenji, Package for semiconductor power device and method for assembling the same.
  31. Yu, Chen-Hua; Hung, Wensen; Huang, Szu-Po; Su, An-Jhih; Lee, Hsiang-Fan; Chen, Kim Hong; Wu, Chi-Hsi; Jeng, Shin-Puu, Packages with thermal interface material on the sidewalls of stacked dies.
  32. Xu, Mingjie; Prstic, Suzana; Dhane, Kedar, Plurality of stiffeners with thickness variation.
  33. Fukuyoshi, Hiroshi; Nakao, Junichi; Endo, Yoshiki; Miyake, Eitaro, Semiconductor device.
  34. Han, Yi Seul; Lee, Tae Yong; Ryu, Ji Yeon, Semiconductor device and method of manufacturing thereof.
  35. Naval, Herbert delos Santos; Sur, Noel A.; Soriano, John A., Semiconductor device having EMI shielding and method therefor.
  36. Berry, Christopher J.; Scanlan, Christopher M., Semiconductor device having RF shielding and method therefor.
  37. Olson, Timothy L.; Scanlan, Christopher M.; Berry, Christopher J., Semiconductor device having RF shielding and method therefor.
  38. Koike, Masahiro; Kurihara, Kenichi, Semiconductor device having heat spreader with center opening.
  39. Bezama, Raschid Jose; Colgan, Evan George; Gaynes, Michael; Magerlein, John Harold; Marston, Kenneth C.; Wei, Xiaojin, Semiconductor package structures having liquid cooler integrated with first level chip package modules.
  40. Chun, Jong Ok; Karim, Nozad; Chen, Richard; Selli, Giuseppe; Kelly, Michael, Shield lid interconnect package and method.
  41. Fuentes, Ruben; Miller, Jr., August Joseph, Shielded electronic component package and method.
  42. Foster, Donald Craig, Shielded package having shield fence.
  43. Foster, Donald Craig, Shielded package having shield lid.
  44. Foster, Donald Craig, Shielded package having shield lid.
  45. Foster, Donald Craig, Shielded package having shield lid.
  46. St. Amand, Roger D.; Karim, Nozad O.; Longo, Joseph M.; Smith, Lee J.; Darveaux, Robert F.; Chun, Jong Ok; Mao, Jingkun, Shielding for a semiconductor package.
  47. Raubo, Roman; Furyk, Marek; Schwartzenberg, John, Silicon devices/heatsinks stack assembly and a method to pull apart a faulty silicon device in said stack assembly.
  48. Wang, Wen-chou Vincent; Li, Yuan; Euzent, Bruce; Mahadev, Vadali, Structure and assembly procedure for low stress thin die flip chip packages designed for low-K Si and thin core substrate.
  49. Fuentes, Ruben; Scanlan, Christopher; Chun, Jong, System and method for RF shielding of a semiconductor package.
  50. Bolognia, David; Kelly, Mike; Smith, Lee, System and method for compartmental shielding of stacked packages.
  51. Kelly, Michael G.; Cambas, John; Tan, Francis; Montero, Pam, System and method for lowering contact resistance of the radio frequency (RF) shield to ground.
  52. Scanlan, Christopher M., System and method for shielding of package on package (PoP) assemblies.
  53. Bolognia, David, System and method to reduce shorting of radio frequency (RF) shielding.
  54. Cheah, Eng C.; Fritz, Donald S., Thermally enhanced metal capped BGA package.
  55. Chun, Jong Ok; Karim, Nozad; Chen, Richard; Selli, Giuseppe; Kelly, Michael, Top feature package and method.
  56. Houle, Sabina J.; Mellody, James P, Underfill process and materials for singulated heat spreader stiffener for thin core panel processing.
  57. Houle, Sabina J.; Mellody, James P, Underfill process and materials for singulated heat spreader stiffener for thin core panel processing.
  58. Houle, Sabina J.; Mellody, James P., Underfill process and materials for singulated heat spreader stiffener for thin core panel processing.
  59. Busch, Diane S., Vapor chamber heat sink with cross member and protruding boss.
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