$\require{mediawiki-texvc}$
  • 검색어에 아래의 연산자를 사용하시면 더 정확한 검색결과를 얻을 수 있습니다.
  • 검색연산자
검색도움말
검색연산자 기능 검색시 예
() 우선순위가 가장 높은 연산자 예1) (나노 (기계 | machine))
공백 두 개의 검색어(식)을 모두 포함하고 있는 문서 검색 예1) (나노 기계)
예2) 나노 장영실
| 두 개의 검색어(식) 중 하나 이상 포함하고 있는 문서 검색 예1) (줄기세포 | 면역)
예2) 줄기세포 | 장영실
! NOT 이후에 있는 검색어가 포함된 문서는 제외 예1) (황금 !백금)
예2) !image
* 검색어의 *란에 0개 이상의 임의의 문자가 포함된 문서 검색 예) semi*
"" 따옴표 내의 구문과 완전히 일치하는 문서만 검색 예) "Transform and Quantization"

통합검색

도움말도움말
상세검색 다국어 입력

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

특허 상세정보

MyON담기
내보내기 페이스북 공유 카카오톡 공유

Apparatus for circuit encapsulation

특허상세정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판) B29C-045/05    B29C-045/14   
미국특허분류(USC) 425/112 ; 425/116 ; 425/129.1 ; 425/544 ; 425/553 ; 564/272.15 ; 564/272.17 ; 564/276
출원번호 US-0802762 (1997-02-20)
발명자 / 주소
출원인 / 주소
대리인 / 주소
    Fish & Richardson P.C.
인용정보 피인용 횟수 : 18  인용 특허 : 42
초록
▼

A circuit on a circuit board is encapsulated using a first mold section and a second mold section. The first mold section closes on one side of the board, and the first mold section has an exposed first conduit. The second mold section closes on another side of the board, and the second mold section has a second conduit for pushing molding compound into a mold cavity in at least one of the mold sections. The second conduit has a side opened to the first mold section when the first and section mold sections are closed on the circuit board. A piston extend...

대표
청구항
▼

[ What is claimed is:] [1.] An apparatus for encapsulating a circuit on a circuit board, comprising:a first mold section configured to close on one side of the board, the first mold section having an exposed cylinder;a second mold section configured to close on another side of the board, the second mold section having a conduit for pushing molding compound into a mold cavity in at least one of the mold sections, the conduit having a exposed portion opened to the exposed cylinder when the first and second mold sections are closed on the board;the exposed ...

이 특허에 인용된 특허 (42)

  1. Chou C. H. (Taipei TWX) Wang T. H. (Taipei Hsien TWX) Chen C. S. (Taipei Hsien TWX). Air exhaust mold plunger. USP1997055626887.
  2. Moitzger Max (Lodi CA). Apparatus for encapsulating selected portions of a printed circuit board. USP1989084861251.
  3. De\Ath Roderick M. (Oxfordshire GB2). Apparatus for injection moulding. USP1989114881884.
  4. Shaheen Joseph M. (La Habra CA). Ceramic/organic multilayer interconnection board. USP1988044740414.
  5. Derryberry Lesli A. (Dallas TX) Williams Charles E. (Dallas TX). Circuit board with a chip carrier and mounting structure connected to the chip carrier. USP1988064750089.
  6. Leatham James G. (Redondo Beach CA). Circuit package attachment apparatus and method. USP1988094769525.
  7. Kaufman Lance R. (131 White Oak Way Mequon WI 53092). Compact circuit package having improved circuit connectors. USP1980084218724.
  8. Fierkens Richard H. J. (Keurbeck 15 6914 Ae Herwen NLX). Compression-cavity mold for plastic encapsulation of thin-package integrated circuit device. USP1994075326243.
  9. Bartley John E. (Greenfield WI) Penrod Orville R. (Kernersville NC). Edge termination for an electrical circuit device. USP1983084400762.
  10. Yamamoto Masato (Imari JPX). Electric device with an operation indicating lamp. USP1990024899257.
  11. Knoll Carl G. (Melrose Park IL). Electrical terminal constructed to prevent insert molding flash. USP1977064029388.
  12. Neugebauer Constantine A. (Schenectady NY) Satriano Robert J. (Hackettstown NJ) Burgess James F. (Schenectady NY) Glascock ; II Homer H. (Scotia NY) Temple Victor A. K. (Clifton Park NY) Watrous Dona. High current hermetic package having a lead extending through the package lid and a packaged semiconductor chip. USP1991075028987.
  13. Wojnarowski Robert J. (Ballston Lake NY) Eichelberger Charles W. (Schenectady NY) Kornrumpf William P. (Albany NY). High density interconnect structure including a chamber. USP1994075331203.
  14. Eichelberger Charles W. (Schenectady NY) Wojnarowski Robert J. (Ballston Lake NY). High density interconnect with high volumetric efficiency. USP1991055019946.
  15. Boucard Michel (Tournefeuille FRX) Thirion Christian (Auterive FRX) Maurel Christian (Toulouse FRX). Housing for an electronic circuit. USP1989114879630.
  16. Werther William E. (Glen Cove NY). Interconnection package suitable for electronic devices and methods for producing same. USP1988064750092.
  17. Gilbert, Barry K.; Schwab, Daniel J.. Leadless chip carrier apparatus providing an improved transmission line environment and improved heat dissipation. USP1985114551746.
  18. Gilbert, Barry K.; Schwab, Daniel J.. Leadless chip carrier apparatus providing for a transmission line environment and improved heat dissipation. USP1985114551747.
  19. Benenati Robert (Tamarac FL) Desjardins Joseph (Tamarac FL) Mitzlaff James E. (Carpentersville IL) Beutler Scott D. (Des Plaines IL) Albert Mike M. (Chicago IL) Brown Vernon L. (Barrington IL). Leadless chip carrier for RF power transistors or the like. USP1988114783697.
  20. Kaufman Lance R. (131 N. White Oak Way Mequon WI 53092). Low cost compressively clamped circuit and heat sink assembly. USP1988024724514.
  21. Hamada Makoto (Tokyo JPX) Ise Hiroshi (Tokyo JPX). Metal mold for sealing semiconductor devices with a resin. USP1994105356283.
  22. Howden Harry (Smallfield GB2). Method and apparatus for producing a lens having an accurately centered aspherical surface. USP1986104615847.
  23. McShane Michael B. (Austin TX) Woosley Alan H. (Austin TX) Primeaux Francis (Austin TX). Method for encapsulating semiconductor devices with package bodies. USP1994095344600.
  24. Goo Lee (Seoul KRX). Method for molding of integrated circuit package. USP1997065637273.
  25. Eichelberger Charles W. (Schenectady NY) Wojnarowski Robert J. (Ballston Lake NY) Welles ; II Kenneth B. (Schenectady NY). Method for packaging integrated circuit chips employing a polymer film overlay layer. USP1990064933042.
  26. Heft Josef (Munich DEX). Method for producing electrical connection with a ribbon cable. USP1985074528749.
  27. Leeb Karl-Erik (Djurhamn SEX). Method of manufacturing circuit board having lateral conductive pattern. USP1994125375322.
  28. Arai Yasunari (Tokyo JPX) Hamano Hiroshi (Kawasaki JPX) Amemiya Izumi (Yokohama JPX) Yamamoto Takuji (Kawasaki JPX) Ihara Takeshi (Kawasaki JPX). Method of producing an electronic circuit package. USP1993055206986.
  29. Chia Chok J. (Santa Clara CA). Molded pin grid array package GPT. USP1987084688152.
  30. Sakai Kunito (Hyogo JPX) Oshio Kazuharu (Hyogo JPX) Kanegae Hirozoh (Hyogo JPX). Molding machine and method. USP1995035395226.
  31. Wolf Franz-Josef (Bad Soden Salmunster DEX). Molding tool. USP1982064336009.
  32. Shimada Yuzo (Tokyo JPX) Kurokawa Yasuhiro (Tokyo JPX) Utsumi Kazuaki (Tokyo JPX). Multi-layer circuit board having a large heat dissipation. USP1988024724283.
  33. Eichelberger Charles W. (Schenectady NY) Wojnarowski Robert J. (Ballston Lake NY). Multichip integrated circuit packaging configuration and method. USP1988114783695.
  34. Eichelberger Charles W. (Schenectady NY) Wojnarowski Robert J. (Ballston Lake NY). Multichip integrated circuit packaging method. USP1990044918811.
  35. Kaufman, Lance R.. Multiple substrate circuit package. USP1985114554613.
  36. Vinciarelli Patrizio (Boston MA) Finnemore Fred (No. Reading MA) Balog John S. (Mendon MA) Johnson Brant T. (Concord MA). Packaging electrical components. USP1994115365403.
  37. Carlson Randolph S. (Carson City NV) Chase Charles P. (Carson City NV). Packaging system for stacking integrated circuits. USP1990084953005.
  38. Chia Chok J. (Santa Clara CA). Plastic molded pin-grid-array power package. USP1989094868349.
  39. Morris James B. (Bloomington MN). Process for assembling integrated circuit packages. USP1988044736520.
  40. Konishi Akira (Kyoto JPX) Wakano Teruo (Kyoto JPX). Semiconductor device and its manufacture. USP1989044823234.
  41. Mennitt Timothy J. (Cedar Park TX) Warren John P. (Austin TX) Sloan James W. (Austin TX). Semiconductor device with test-only contacts and method for making the same. USP1994085334857.
  42. Calver John G. (Rochester NY) Pearce Phillip W. (Pavilion NY) Zielinski Erich (Bergen NY). Semiconductor mounting assembly. USP1987094691265.

이 특허를 인용한 특허 피인용횟수: 18

  1. Karmazyn, Michael J.. Angular encapsulation of tandem stacked printed circuit boards. USP2010057712213.
  2. Ahmad,Syed Sajid. Interconnecting substrates for electrical coupling of microelectronic components. USP2006016983551.
  3. Ahmad,Syed Sajid. Interconnecting substrates for electrical coupling of microelectronic components. USP2006016982386.
  4. Hauser, Christian; Schmidt, Helge; Winderl, Johann. Lead frame for the installation of an integrated circuit in an injection-molded package. USP2003096614100.
  5. Bolken, Todd O.. Method and apparatus for packaging a microelectronic die. USP2003126664139.
  6. Bolken, Todd O.. Method and apparatus for packaging a microelectronic die. USP2003116653173.
  7. Bolken, Todd O.. Method and apparatus for packaging a microelectronic die. USP2004016683388.
  8. Ahmad, Syed Sajid. Method of Interconnecting substrates for electrical coupling of microelectronic components. USP2004096796028.
  9. Cobbley,Chad A.. Method of encapsulating interconnecting units in packaged microelectronic devices. USP2006097101737.
  10. Cobbley,Chad A.. Method of encapsulating packaged microelectronic devices with a barrier. USP2008027332376.
  11. Farnworth,Warren M.; Wood,Alan G.. Methods for forming protective layers on semiconductor device substrates. USP2006087084013.
  12. Bolken, Todd O.. Microelectronic devices and microelectronic die packages. USP2004016677675.
  13. Cobbley, Chad A.. Packaged microelectronic devices with interconnecting units. USP2005016838760.
  14. James, Stephen L.; Cobbley, Chad A.. Packaged microelectronic devices with pressure release elements and methods for manufacturing and using such packaged microelectronic devices. USP2005126979595.
  15. James,Stephen L.; Cobbley,Chad A.. Packaged microelectronic devices with pressure release elements and methods for manufacturing and using such packaged microelectronic devices. USP2006057049685.
  16. Farnworth,Warren M.; Wood,Alan G.. Semiconductor devices including protective layers on active surfaces thereof. USP2006067067901.
  17. Farnworth, Warren M.; Wood, Alan G.. Stereolithographic methods for forming a protective layer on a semiconductor device substrate and substrates including protective layers so formed. USP2005046875640.
  18. Farnworth, Warren M.. Systems and methods for compressing an encapsulant adjacent a semiconductor workpiece. USP2010117833456.

IPC 상위 출원인