초록 ▼

A vector/scalar computer system has nodes interconnected by an interconnect network. Each node includes a vector execution unit, a scalar execution unit, physical vector registers holding physical vector elements, a mapping vector register holding a mapping vector, and a memory. The physical vector

A vector/scalar computer system has nodes interconnected by an interconnect network. Each node includes a vector execution unit, a scalar execution unit, physical vector registers holding physical vector elements, a mapping vector register holding a mapping vector, and a memory. The physical vector registers from nodes together form an architectural vector register having architectural vector elements. The mapping vector defines an assignment of architectural vector elements to physical vector elements for its node. The memories from the nodes together form an aggregate memory.

대표청구항 ▼

[ What is claimed is:] [1.] A vector/scalar computer system comprising:a plurality of processing element nodes, each processing element node includes:a vector execution unit,a scalar execution unit,physical vector registers holding physical vector elements, wherein physical vector registers from the

[ What is claimed is:] [1.] A vector/scalar computer system comprising:a plurality of processing element nodes, each processing element node includes:a vector execution unit,a scalar execution unit,physical vector registers holding physical vector elements, wherein physical vector registers from the plurality of processing element nodes together form an architectural vector register having architectural vector elements,a mapping vector register holding a mapping vector defining an assignment of architectural vector elements to physical vector elements for its node, anda memory, wherein memories from the plurality of processing element nodes together form an aggregate memory; andan interconnect network interconnecting the processing element nodes.