초록 ▼

A data mover which provides guaranteed transfer of data between two locations. The data mover includes a pair of data packet memories for input, a pair of data packet memories for output, and a controller which alternately switches each of the paired data packet memories between a data loading mode

A data mover which provides guaranteed transfer of data between two locations. The data mover includes a pair of data packet memories for input, a pair of data packet memories for output, and a controller which alternately switches each of the paired data packet memories between a data loading mode and a data unloading mode. The controller enables one of the paired data packet memories in the data loading mode and enables the other one of the paired data packet memories in the data unloading mode. The controller switches the modes of the paired data packet memories upon receiving an acknowledgement of moved data. By (a) switching the paired data packet memories upon receiving the acknowledgement, (b) segmenting the data packets (enabling data transfer initiation before all source data becomes available) and/or (c) embedding a response (enabling transmission of the next packet without first waiting for complete transmission of an incoming packet), complete transmission of the bi-directional data is automatically segmented and reassembled to minimize latency.

대표청구항 ▼

[ What is claimed:] [1.] A data mover for moving a plurality of data packets between a first host and a second host, said data mover comprising:first and second transmit data packet memories each configured to hold one of said plurality of data packets at a time;a transmitter for transmitting data t

[ What is claimed:] [1.] A data mover for moving a plurality of data packets between a first host and a second host, said data mover comprising:first and second transmit data packet memories each configured to hold one of said plurality of data packets at a time;a transmitter for transmitting data to the second host; anda controller in communication with said first and second transmit data packet memories and said transmitter, said controller for alternately enabling one of said first and second transmit data packet memories to receive a first one of said data packets from the first host while enabling the other of said first and second transmit data packet memories to transfer a second one of said data packets to said transmitter.