초록 ▼

Object-code compatibility is provided among VLIW processors with different organizations. The object-code can also be executed by sequential processors, thus providing compatibility with scalar and superscalar processors, A mechanism is provided which allows representing VLIW programs in an implemen

Object-code compatibility is provided among VLIW processors with different organizations. The object-code can also be executed by sequential processors, thus providing compatibility with scalar and superscalar processors, A mechanism is provided which allows representing VLIW programs in an implementation-independent manner. This mechanism relies on instruction cache (I-cache) reload/access logic which incorporates implementation-dependent features into a VLIW program. In this way, programs are represented in main memory in an implementation-independent manner, the implementation-specific aspects are introduced as part of the instruction cache reload/fetch processes, and the simplicity in instruction dispatch logic that is characteristic of VLIW processors is preserved. The foregoing allows for object-code compatibility among VLIW processors with different organizations. Also provided is a mechanism and an apparatus for the interpretation of tree-instructions by a computer system based on a VLIW processor.

대표청구항 ▼

[ Having thus described my invention, what I claim and desire to secure by Letters Patent is as follows:] [1.] A method of executing a program, said method comprising the steps of:constructing a program as a set of variable length tree-instructions, each given tree-instruction comprising a sequence

[ Having thus described my invention, what I claim and desire to secure by Letters Patent is as follows:] [1.] A method of executing a program, said method comprising the steps of:constructing a program as a set of variable length tree-instructions, each given tree-instruction comprising a sequence of primitive instructions including at least one execution path which are subject to sequential semantics, wherein each execution path starting at a first primitive instruction of said sequence of primitive instructions for said given tree-instruction and terminating at an unconditional branch instruction to a target instruction outside of said tree-instruction;storing said program in memory, wherein, for each given tree-instruction, said sequence of primitive instructions for said given tree-instruction are stored in consecutive memory locations;accessing said memory to fetch a memory block;decomposing portions of at least one tree-instruction stored in said memory block into a plurality of variable length intermediate instructions according to resources of a processor;executing said variable-length intermediate instructions in said processor.