초록 ▼

A pair of complementary CJIGFETs (100 and 160) are created from a body of semiconductor material (102 and 104). Each CJIGFET is formed with (a) a pair of laterally separated source/drain zones (112 and 114 or 172 and 174) situated along the upper surface of the semiconductor body, (b) a channel regi

A pair of complementary CJIGFETs (100 and 160) are created from a body of semiconductor material (102 and 104). Each CJIGFET is formed with (a) a pair of laterally separated source/drain zones (112 and 114 or 172 and 174) situated along the upper surface of the semiconductor body, (b) a channel region (110 or 170) extending between the source/drain zones, and (c) a gate electrode (118 or 178) overlying, and electrically insulated from, the channel region. The gate electrode of each CJIGFET has a Fermi energy level within 0.3 ev of the middle of the energy band gap of the semiconductor material. One of the transistors typically conducts current according to a field-induced-channel mode while the other transistor conducts current according to a metallurgical-channel mode. The magnitude of the threshold voltage for each CJIGFET is normally no more than 0.5 V.

대표청구항 ▼

[ We claim:] [1.] A complementary-transistor structure comprising:a body of semiconductor material having an upper semiconductor surface, the semiconductor material characterized by an electron affinity .chi..sub.S and a valence-to-conduction band-gap energy E.sub.G ; andcomplementary first and seco

[ We claim:] [1.] A complementary-transistor structure comprising:a body of semiconductor material having an upper semiconductor surface, the semiconductor material characterized by an electron affinity .chi..sub.S and a valence-to-conduction band-gap energy E.sub.G ; andcomplementary first and second field-effect transistors, each comprising:a pair of laterally separated source/drain zones situated in the semiconductor body along the upper semiconductor surface;a channel region extending between the source/drain zones in the semiconductor body along the upper semiconductor surface; anda gate electrode overlying the channel region, electrically insulated from the channel region, and having a work function within 0.3 eV of .chi..sub.S +E.sub.G /2; where the source/drain zones and channel region of the first transistor are of a first conductivity type, and the source/drain zones and channel region of the second transistor are of a second conductivity type opposite to the first conductivity type.