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Pin attach structure for an electronic package 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/532
출원번호 US-0842859 (1997-04-16)
발명자 / 주소
  • Dibble Eric P.
  • Laine Eric H.
  • MacQuarrie Stephen W.
출원인 / 주소
  • International Business Machines Corporation
대리인 / 주소
    Ratner & PrestiaPivnichny
인용정보 피인용 횟수 : 15  인용 특허 : 22

초록

A pinning process including the steps of gold-plating through-holes in a laminate carrier and crimping a gold or gold-plated pin located in the through-holes to form a pin head on the top and a pin bulge on the bottom of the laminate carrier to produce a plastic pin grid array. A variety of mechanic

대표청구항

[ What is claimed:] [1.] A plastic pin grid array comprising a laminate carrier having a top surface and a bottom surface, a centrally disposed dielectric material, and at least one transverse through-hole which defines an inner surface with a corresponding at least one pin inserted therein and havi

이 특허에 인용된 특허 (22)

  1. Rogers Wesley D. (Huntsville AL) Hard Douglas G. (Fayetteville TN), Cross-connect system.
  2. Nye ; III Henry A. (Bedford NY) Roeder Jeffrey F. (Brookfield CT) Tong Ho-Ming (Yorktown Heights NY) Totta Paul A. (Poughkeepsie NY), Electroplated solder terminal.
  3. Cray Seymour R. (Chippewa Falls WI) Krajewski Nicholas J. (Elk Mound WI), Flying leads for integrated circuits.
  4. Cohn Charles (Wayne NJ), Integrated circuit package using plastic encapsulant.
  5. Lee James C. K. (Los Altos Hills CA), Integrated circuit packaging systems with double surface heat dissipation.
  6. Cray Seymour R. (Chippewa Falls WI) Krajewski Nicholas J. (Elk Mound WI), Lead bonding of chips to circuit boards and circuit boards to circuit boards.
  7. Saban John F. (Lyons IL), Lead-receiving socket, multi-socket assembly incorporating same and method of effecting circuit interconnections therewi.
  8. Ohno Jun-ichi (Yokohama JPX) Fukazawa Koh-ichi (Tokyo JPX) Shindo Masamichi (Yokohama JPX), Method of making a semiconductor device having lead pins and a metal shell.
  9. Grabbe Dimitry G. (Middletown PA) Korsunsky Iosif (Harrisburg PA), Method of making contact surface for contact element.
  10. Komathu Kathuzi (Kawagoe JPX), Method of molding a protective cover on a pin grid array.
  11. Chia Chok J. (Santa Clara CA), Molded pin grid array package GPT.
  12. Currie Thomas P. (St. Paul MN) Goldberg Norman (Dresher PA), Multichip thin film module.
  13. McShane Michael B. (Austin TX) Lin Paul T. (Austin TX) Wilson Howard P. (Austin TX), Packaged semiconductor device having a low cost ceramic PGA package.
  14. Bronson Lance A. (Port Crane NY) Moore Scott P. (Apalachin NY) Shriver ; III John A. (Owego NY), Pinned ceramic chip carrier.
  15. Theobald Paul R. (Signal Mountain TN), Plastic chip carrier package.
  16. Muehling Richard (Cranston RI), Plastic pin grid array chip carrier.
  17. Cohn Charles (Wayne NJ), Plastic pin grid array package.
  18. Lin Paul T. (Austin TX), Process for making a hermetic low cost pin grid array package.
  19. Bridges William G. (Meriden CT) Armer Thomas A. (New Haven CT) Chang Kin-Shiung (Meriden CT), Process for manufacturing plastic pin grid arrays and the product produced thereby.
  20. Sugimoto Masahiro (Yokosuka JPX) Wakasugi Yasumasa (Kawasaki JPX) Harada Shigeki (Kawasaki JPX), Semiconductor device and method of producing semiconductor device.
  21. Grabbe Dimitry G. (Middletown PA) Granitz Richard F. (Harrisburg PA), Surface mounting an electronic component.
  22. Grabow Wilhelm (Nordstemmen DEX) Bode Friedrich-Wilhelm (Apelern DEX), System for bidirectional data transmission between a beacon and a vehicle.

이 특허를 인용한 특허 (15)

  1. Kim, Tae Jun; Song, Yoo Sun, Chip on board package for optical mice and lens cover for the same.
  2. Pitzele, Lennart, Flanged terminal pins for DC/DC converters.
  3. Pitzele,Lennart, Flanged terminal pins for DC/DC converters.
  4. Pitzele, Lennart, Flanged terminal pins for dc/dc converters.
  5. Roberts, Stuart L.; Reynolds, Tracy V.; Fogal, Rich; Schwab, Matt E., Packaged microdevices and methods for manufacturing packaged microdevices.
  6. Roberts, Stuart L.; Reynolds, Tracy V.; Fogal, Rich; Schwab, Matt E., Packaged microdevices and methods for manufacturing packaged microdevices.
  7. Roberts, Stuart L.; Reynolds, Tracy V.; Fogal, Rich; Schwab, Matt E., Packaged microdevices and methods for manufacturing packaged microdevices.
  8. Eric P. Dibble ; Eric H. Laine ; Stephen W. MacQuarrie, Process of producing plastic pin grid array.
  9. Farnworth,Warren M.; Wood,Alan G.; Doan,Trung Tri, Semiconductor component having thinned die with conductive vias configured as conductive pin terminal contacts.
  10. Farnworth,Warren M.; Wood,Alan G.; Doan,Trung Tri, Semiconductor component having thinned die, polymer layers, contacts on opposing sides, and conductive vias connecting the contacts.
  11. Farnworth,Warren M.; Wood,Alan G.; Doan,Trung Tri, Semiconductor component sealed on five sides by polymer sealing layer.
  12. Farnworth, Warren M.; Wood, Alan G.; Doan, Trung Tri, Semiconductor components and methods of fabrication with circuit side contacts, conductive vias and backside conductors.
  13. Ooyabu, Yasunari; Ohsawa, Tetsuya; Tani, Emiko, Suspension board and load beam combination including a positioning reference hole and a reinforcing layer.
  14. Ooyabu, Yasunari; Ohsawa, Tetsuya; Tani, Emiko, Suspension board with circuit, producing method thereof, and positioning method of suspension board with circuit.
  15. Coon,Warren, Suspension with no-solder, no-resin conductor extending through insulator-spaced metal layers.
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