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Dissolvable dielectric method 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/4763
출원번호 US-0659166 (1996-06-05)
발명자 / 주소
  • Hause Fred N.
  • Bandyopadhyay Basab
  • Dawson Robert
  • Fulford
  • Jr. H. Jim
  • Michael Mark W.
  • Brennan William S.
출원인 / 주소
  • Advanced Micro Devices, Inc.
대리인 / 주소
    Daffer
인용정보 피인용 횟수 : 97  인용 특허 : 25

초록

A fabrication process that produces an air gap dielectric in which a multi-level interconnect structure is formed upon a temporary supporting material. The temporary material is subsequently dissolved away leaving behind an intralevel and an interlevel dielectric comprised of air. In one embodiment

대표청구항

[ What is claimed is:] [1.] A method of fabricating interconnect levels on a semiconductor substrate comprising:forming a barrier layer on said substrate;forming a first interconnect level on said barrier layer wherein said first interconnect level comprises a plurality of substantially coplanar fir

이 특허에 인용된 특허 (25)

  1. Bartelink Dirk J. (13170 La Cresta Dr. Los Altos Hills CA 94022), Air-dielectric transmission lines for integrated circuits.
  2. Lien Chuen-Der (Mountain View CA) Lee Jimmy J. (Palo Alto CA) Liao Daniel J. L. (Pleasanton CA) Santandrea Joe F. (Los Altos Hills CA), Conductor capacitance reduction in integrated circuits.
  3. Satoh Shinichi (Hyogo JPX) Ozaki Hiroji (Hyogo JPX) Eimori Takahisa (Hyogo JPX), Field effect transistor with T-shaped gate electrode and manufacturing method therefor.
  4. Thomas Michael E. (Cupertino CA) Chinn Jeffrey D. (Foster City CA), High performance interconnect system for an integrated circuit.
  5. Moslehi Mehrdad M., Insulated-gate field-effect transistor structure and method.
  6. Aitken John M. (Mahopac NY) Beyer Klaus D. (Poughkeepsie NY) Crowder Billy L. (Putnam Valley NY) Greco Stephen E. (Lagrangeville NY), Larce scale IC personalization method employing air dielectric structure for extended conductors.
  7. Cho Chin-Chen (Richardson TX), Low dielectric constant insulation in VLSI applications.
  8. Chang Mark S. (Los Altos CA) Cheung Robin W. (Cupertino CA), Method of decreased interlayer dielectric constant in a multilayer interconnect structure to increase device speed perfo.
  9. Potter Curtis N. (Austin TX) Smith Lawrence N. (Austin TX) Kroger Harry (Austin TX), Method of fabricating a high density electrical interconnect.
  10. Fulford ; Jr. H. Jim ; Dawson Robert ; Hause Fred N. ; Bandyopadhyay Basab ; Michael Mark W. ; Brennan William S., Method of formation of an air gap within a semiconductor dielectric by solvent desorption.
  11. Fitch Jon T. (Austin TX) Maniar Papu (Austin TX) Witek Keith E. (Austin TX) Gelatos Jerry (Austin TX) Moazzami Reza (Austin TX) Ajuria Sergio A. (Austin TX), Method of forming a semiconductor structure having an air region.
  12. Stoltz Richard A. (Plano TX) Tigelaar Howard (Allen TX) Cho Chih-Chen (Richardson TX), Method of forming air gap dielectric spaces between semiconductor leads.
  13. Yee Ian Y. K. (Austin TX), Method of making a multilevel electrical airbridge interconnect.
  14. Taniguchi Akihisa (Itami JPX), Method of making field effect transistor with T-shaped gate electrode.
  15. Lur Water (Taipei TWX) Wu J. Y. (Dou-Lio TWX), Method of making stress released VLSI structure by the formation of porous intermetal layer.
  16. Eldridge Benjamin N. ; Grube Gary W. ; Khandros Igor Y. ; Mathieu Gaetan L., Method of making temporary connections between electronic components.
  17. Cho Byung J. (Kyungki-Do KRX), Method of manufacturing a semiconductor device.
  18. van Laarhoven Josephus M. F. G. (Groenewoudseweg 1 Eindhoven) Gootzen Wilhelmus F. M. (Groenewoudseweg 1 Eindhoven NLX) Bellersen Michael F. B. (Reemstckenkamp 3c Hamburg DEX 2000) Doan Trung T. (157, Method of manufacturing a semiconductor device by forming insulating side walls with voids below overhangs.
  19. Wada Masaru (Takatsuki JPX) Shimizu Hirokazu (Suita JPX) Shibutani Takao (Takatsuki JPX) Itoh Kunio (Uji JPX) Hamada Ken (Toyonaka JPX) Teramoto Iwao (Ibaraki JPX), Method of manufacturing semiconductor device.
  20. Dawson Robert ; Michael Mark W. ; Brennan William S. ; Bandyopadhyay Basab ; Fulford ; Jr. H. Jim ; Hause Fred N., Multilevel interconnect structure of an integrated circuit having air gaps and pillars separating levels of interconnec.
  21. Orlowski Marius K. ; Baker ; Jr. Frank Kelsey, Process for forming a transistor with a nonuniformly doped channel.
  22. Cohen Jerome (Centerville OH) Chen Peter C. (Sunnyvale CA), Process for minimum overlap silicon gate devices.
  23. Finnila Ronald M. (Carlsbad CA), Process of manufacturing a three dimensional integrated circuit from stacked SOI wafers using a temporary silicon substr.
  24. Kurtz Anthony D. (Teaneck NJ) Shor Joseph S. (Flushing NY) Ned Alexander A. (Bloomingdale NJ), Semiconductor structures having environmentally isolated elements and method for making the same.
  25. Lur Water (Taipei TWX) Houn Edward (Tainan TWX), Stress relaxation in dielectric before metalization.

이 특허를 인용한 특허 (97)

  1. Liu Erzhuang,SGX, Air gap formation for high speed IC processing.
  2. Wei,John Shi Sun; Parkhurst,Ray Myron; Jennison,Michael James; Nikkel,Philip Gene, Airdome enclosure for components.
  3. Dubin, Valery M.; Moon, Peter K., Apparatus for an improved air gap interconnect structure.
  4. Nowak Edward D. ; Bothra Subhas, Apparatus for automated pillar layout.
  5. Lee, Jin-Yuan; Lin, Mou-Shiung; Huang, Ching-Cheng, Chip structure and process for forming the same.
  6. Lee, Jin-Yuan; Lin, Mou-Shiung; Huang, Ching-Cheng, Chip structure and process for forming the same.
  7. Lin, Mou-Shiung; Lee, Jin-Yuan; Huang, Ching-Cheng, Chip structure and process for forming the same.
  8. Lin, Mou-Shiung; Lee, Jin-Yuan; Huang, Ching-Cheng, Chip structure and process for forming the same.
  9. Sandhu, Gurtej S.; Durcan, D. Mark, Devices with nanocrystals and methods of formation.
  10. Sandhu, Gurtej S.; Durcan, D. Mark, Devices with nanocrystals and methods of formation.
  11. H. Jim Fulford, Jr. ; Robert Dawson ; Fred N. Hause ; Basab Bandyopadhyay ; Mark W. Michael ; William S. Brennan, Dielectric having an air gap formed between closely spaced interconnect lines.
  12. Ahn,Kie Y.; Forbes,Leonard, Electronic apparatus with deposited dielectric layers.
  13. Lin, Mou-Shing, High performance system-on-chip using post passivation process.
  14. Lin, Mou-Shiung, High performance system-on-chip using post passivation process.
  15. Farrar,Paul A., Hydrophobic foamed insulators for high density circuits.
  16. Farrar, Paul A., Insulators for high density circuits.
  17. Farrar, Paul A., Insulators for high density circuits.
  18. Gardner Mark I. ; Spikes Thomas E. ; Paiz Robert, Integrated circuit utilizing an air gap to reduce capacitance between adjacent metal linewidths.
  19. Ahn, Kie Y., Integrated circuit wiring with low RC time delay.
  20. Bandyopadhyay Basab ; Fulford ; Jr. H. Jim ; Dawson Robert ; Hause Fred N. ; Michael Mark W. ; Brennan William S., Interlevel dielectric with air gaps to lessen capacitive coupling.
  21. Farrar, Paul A., Low dielectric constant STI with SOI devices.
  22. Farrar, Paul A., Low dielectric constant STI with SOI devices.
  23. Farrar, Paul A., Low dielectric constant shallow trench isolation.
  24. Farrar, Paul A., Low dielectric constant shallow trench isolation.
  25. Farrar, Paul A., Low dielectric constant shallow trench isolation.
  26. Farrar, Paul A., Low dielectric constant shallow trench isolation.
  27. Farrar, Paul A., Low dielectric constant shallow trench isolation.
  28. Paul A. Farrar, Low dielectric constant shallow trench isolation.
  29. Buynoski, Matthew S., Low dielectric metal silicide lined interconnection system.
  30. Buynoski Matthew S., Low dielectric semiconductor device with rigid, conductively lined interconnection system.
  31. Farrar, Paul A., Memory system with conductive structures embedded in foamed insulator.
  32. Dubin,Valery M.; Moon,Peter K., Method and apparatus for an improved air gap interconnect structure.
  33. Dubin, Valery M.; Moon, Peter K., Method for an improved air gap interconnect structure.
  34. Demolliens, Olivier; Berruyer, Pascale; Trouiller, Yorick; Morand, Yves, Method for fabricating a structure of interconnections comprising an electric insulation including air or vacuum gaps.
  35. Victor Seng Keong Lim SG; Young-Way Teh SG; Ting-Cheong Ang SG; Alex See SG; Yong Kong Siew MY, Method for fabricating an air gap shallow trench isolation (STI) structure.
  36. Lin, Mou-Shiung; Lee, Jin-Yuan; Huang, Ching-Cheng, Method for fabricating circuitry component.
  37. Ahn,Kie Y.; Forbes,Leonard, Method for making integrated circuits.
  38. Ahn,Kie Y., Method of fabricating a semiconductor interconnect structure.
  39. Stephen Keetai Park, Method of fabricating copper-based semiconductor devices using a sacrificial dielectric layer.
  40. Buynoski Matthew S., Method of forming low dielectric semiconductor device with rigid, metal silicide lined interconnection system.
  41. Taguchi Mitsuru,JPX ; Maeda Keiichi,JPX, Method of forming wirings.
  42. Lin, Charles, Method of making an ultimate low dielectric device.
  43. Ahn, Kie Y.; Forbes, Leonard, Methods and apparatus for making integrated-circuit wiring from copper, silver, gold, and other metals.
  44. Kevin S. Petrarca ; Rebecca D. Mih, Microprocessor having air as a dielectric and encapsulated lines.
  45. Petrarca Kevin S. ; Mih Rebecca D., Microprocessor having air as a dielectric and encapsulated lines and process for manufacture.
  46. Ahn,Kie Y.; Forbes,Leonard, Multilevel copper interconnects with low-k dielectrics and air gaps.
  47. Farrar,Paul A., Packaging of electronic chips with air-bridge structures.
  48. Farrar,Paul A., Packaging of electronic chips with air-bridge structures.
  49. Farrar, Paul A., Polynorbornene foam insulation for integrated circuits.
  50. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
  51. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
  52. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
  53. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
  54. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
  55. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
  56. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chips.
  57. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation method for semiconductor chip or wafer.
  58. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation structure for semiconductor chip or wafer.
  59. Pendo, Shaun; Shah, Rajiv; Chernoff, Edward, Sensor substrate and method of fabricating same.
  60. Pendo, Shaun; Shah, Rajiv; Chernoff, Edward, Sensor substrate and method of fabricating same.
  61. Agarwal,Vishnu K.; Sandhu,Gurtej, Structurally-stabilized capacitors and method of making of same.
  62. Farrar, Paul A., Structures and methods to enhance copper metallization.
  63. Maury Alvaro ; Miceli Frank ; Karthikeyan Subramanian, Test structures for testing planarization systems and methods for using same.
  64. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  65. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  66. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  67. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
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  90. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  91. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  92. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  93. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  94. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  95. Mou-Shiung Lin TW, Top layers of metal for high performance IC's.
  96. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Top layers of metal for integrated circuits.
  97. Ahn, Kie Y.; Forbes, Leonard, Zirconium-doped tantalum oxide films.
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