초록 ▼

A high performance digital signal processor includes a memory for storing instructions and operands for digital signal computations and a core processor connected to the memory. The memory includes first, second and third memory banks connected to the core processor by first, second and third data a

A high performance digital signal processor includes a memory for storing instructions and operands for digital signal computations and a core processor connected to the memory. The memory includes first, second and third memory banks connected to the core processor by first, second and third data and address buses, respectively. The core processor includes a program sequencer and first and second computation blocks for performing first and second subsets, respectively, of the digital signal computations. Single, dual or quad data words of 32 bits each may be accessed in each of the memory banks during each clock cycle. The multiple data words may be transferred to one or both of the first and second computation blocks.

대표청구항 ▼

[ What is claimed is:] [20.] A method for digital signal processing comprising the steps of:storing instructions for digital signal computations in a first memory bank and storing operands for the digital signal computations in a second memory bank;generating instruction addresses for fetching selec

[ What is claimed is:] [20.] A method for digital signal processing comprising the steps of:storing instructions for digital signal computations in a first memory bank and storing operands for the digital signal computations in a second memory bank;generating instruction addresses for fetching selected ones of said instructions from said first memory bank;simultaneously addressing quad operands in a single row of said second memory bank and selectably and simultaneously providing one, two or four of said quad operands to a computation unit for performing said digital signal computations, said computation unit including a first computation block for performing a first subset of said digital signal computations using a first subset of said instructions and a first subset of said operands, and a second computation block for performing a second subset of said digital signal computations using a second subset of said instructions and a second subset of said operands, wherein said second memory bank is organized as quad word rows and wherein the steps of simultaneously addressing quad operands and selectably and simultaneously providing one, two or four of said quad operands include accessing single, dual or quad locations in a selected quad row and each of said first and second computation blocks selects the operands accessed in said second memory bank; andsaid computation unit performing said digital signal computations using said instructions from said first memory bank and said operands from said second memory bank.