초록 ▼

A programmable delay circuit employs a comparator to control an output driver. The comparator compares a ramp signal to an error control signal derived from an error amplifier or in the alternative to a disable signal. The output of the comparator is latched on until a reset signal is received. The

A programmable delay circuit employs a comparator to control an output driver. The comparator compares a ramp signal to an error control signal derived from an error amplifier or in the alternative to a disable signal. The output of the comparator is latched on until a reset signal is received. The reset signal is produced when the ramp signal is discharged below a predetermined level. The programmable delay circuit is useful in a secondary side post regulator to control a totem pole driver. The totem pole driver in turn controls a switching device coupled to a voltage on a secondary winding.

대표청구항 ▼

[ We claim:] [1.] An integrated circuit comprising:an error amplifier, connected to receive a voltage sense signal and a reference signal, so as to produce an error control signal;a ramp node for providing a periodic ramp signal;a reset signal generator arranged so as to produce a reset signal;a com

[ We claim:] [1.] An integrated circuit comprising:an error amplifier, connected to receive a voltage sense signal and a reference signal, so as to produce an error control signal;a ramp node for providing a periodic ramp signal;a reset signal generator arranged so as to produce a reset signal;a comparator connected to receive the error control signal and the ramp signal for generating a first state signal or a second state signal depending upon a comparison between the error control signal and the ramp signal;a latch circuit coupled to said reset signal generator and to said comparator in order to latch the first state signal until the reset signal is received; andan output driver, connected to a first terminal and a second terminal, switched in response to the first and second state signals to drive an output signal on the first terminal in response to the first state signal and to provide a low impedance path between the first terminal and the second terminal in response to the second state signal.