초록 ▼

A method and apparatus for optimizing a circuit design having multi-cycle paths therein. In an exemplary embodiment, a circuit design having a number of multi-cycle paths may be optimized by: identifying at least one of the number of multi-cycle paths within the circuit design, and identifying the c

A method and apparatus for optimizing a circuit design having multi-cycle paths therein. In an exemplary embodiment, a circuit design having a number of multi-cycle paths may be optimized by: identifying at least one of the number of multi-cycle paths within the circuit design, and identifying the corresponding qualified clocks associated therewith; replacing selected ones of the corresponding clocks with replacement clocks; and optimizing the circuit design using the replacement clocks. By using a replacement clock that has a clock period equal to the corresponding clock, which is typically a qualified clock, a standard optimization tool may correctly optimize the circuit design.

대표청구항 ▼

[ What is claimed is:] [1.] A method for optimizing a circuit design having a number of multi-cycle paths therein, the method comprising the steps of:identifying at least one of the number of multi-cycle paths within the circuit design, wherein each of the identified multi-cycle paths is controlled

[ What is claimed is:] [1.] A method for optimizing a circuit design having a number of multi-cycle paths therein, the method comprising the steps of:identifying at least one of the number of multi-cycle paths within the circuit design, wherein each of the identified multi-cycle paths is controlled at least in part by a corresponding qualified clock signal, each of the qualified clock signals being generated by one or more gating blocks that logically combine a corresponding raw clock signal having a raw clock period and a phase with at least one other signal so that the corresponding qualified clock signal has a selectively extendable clock period and phase;replacing selected ones of the qualified clock signals with a corresponding replacement clock signal, wherein each of the replacement clock signals have a clock period and a phase that corresponds to the selectively extendable clock period and phase of the corresponding qualified clock signals; andoptimizing the circuit design using selected replacement clock signals.