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Clock signal from an adjustable oscillator for an integrated circuit

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G11C-007/00
출원번호 US-0877253 (1997-06-17)
발명자 / 주소
  • Norman Robert D.
  • Chevallier Christophe J.
출원인 / 주소
  • Micron Technology, Inc.
대리인 / 주소
    Schwegman, Lundberg Woessner & Kluth P.A.
인용정보 피인용 횟수 : 87  인용 특허 : 21

초록

An integrated circuit is described which has circuitry to detect environmental conditions such as temperature and supply voltage and adjust the operation of the circuit accordingly. A flash memory system is described which includes a temperature detector and a supply voltage detector. The memory mon

대표청구항

[ What is claimed is:] [1.] An integrated circuit comprising:an adjustable oscillator circuit for producing a clock signal that controls multiple functions of the integrated circuit;multiple sensors for detecting multiple dynamic parameters of the integrated circuit;a lookup table containing data re

이 특허에 인용된 특허 (21)

  1. Manning Troy A. (Boise ID), Circuit including DRAM and voltage regulator, and method of increasing speed of operation of a DRAM.
  2. Landgraf Marc E. (Folsom CA) Javanifard Jahanshir J. (Sacramento CA) Winston Mark D. (El Dorado Hills CA), Circuitry for power supply voltage detection and system lockout for a nonvolatile memory.
  3. Bailey Joseph A. (Austin TX), Clock control technique and system for a microprocessor including a thermal sensor.
  4. Keeth Brent (Boise ID), Control circuit responsive to its supply voltage level.
  5. Manning Troy A. (Boise ID), Controlling dynamic memory refresh cycle time.
  6. Tillinghast Charles W. (Boise ID) Cohen Michael S. (Boise ID) Voshell Thomas W. (Boise ID), Dynamic RAM array for emulating a static RAM array.
  7. Tobita Youichi (Hyogo JPX), Dynamic random access memory having a plurality of rated voltages as operation supply voltage and operating method there.
  8. Chern Wen-Foo (Boise ID), High efficiency charge pump.
  9. Schutz Joseph D. (Portland OR) Rash Bill C. (Saratoga CA), Integrated circuit device that selects its own supply voltage by controlling a power supply.
  10. Wojciechowski Kenneth E. (Folsom CA), Low current reduced area programming voltage detector for flash memory.
  11. Irrinki V. Swamy ; Kapoor Ashok ; Leung Raymond ; Owens Alex ; Wik Thomas R., Memory system including an on-chip temperature sensor for regulating the refresh rate of a DRAM array.
  12. Ware Frederick A. (Los Altos Hills CA) Gasbarro James A. (Mountain Vew CA) Dillon John B. (Palo Alto CA) Farmwald Michael P. (Portola Valley CA) Horowitz Mark A. (Palo Alto CA) Griffin Matthew M. (Mo, Method and apparatus for implementing refresh in a synchronous DRAM system.
  13. Jungroth Owen (Sonora CA) Price Thomas C. (Fair Oaks CA), Nonvolatile memory with automatic power supply configuration.
  14. Chevallier Christophe J. (Palo Alto CA) Roohparvar Frankie F. (Cupertino CA) Briner Michael S. (San Jose CA), Power level detection circuit.
  15. Dhong Sang H. (Mahopac NY) Shin Hyun J. (Mahopac NY) Hwang Wei (Armonk NY), Power supply tracking regulator for a memory array.
  16. Jeong Dong Sik (Kyoungki-do KRX), Self-refresh period adjustment circuit for semiconductor memory device.
  17. Furuno Takeshi (Kodaira JPX) Nakamura Yasuhiro (Kodaira JPX) Matsuo Akinori (Higashiyamato JPX), Semiconductor integrated circuit operable and programmable at multiple voltage levels.
  18. Yoo Seung-Moon (Suwon KRX) Haq Ejaz ul (Seoul KRX) Choi Yun-Ho (Suwon KRX) Cho Soo-In (Seoul KRX) Chin Dae-Je (Seoul KRX) Kang Nam-Soo (Suwon KRX) Lee Seung-Hun (Suwon KRX), Semiconductor memory device.
  19. Inagaki Yasaburo (Tokyo JPX), Semiconductor memory device with variable self-refresh cycle.
  20. Tillinghast Charles W. (Boise ID) Cohen Michael S. (Boise ID) Voshell Thomas W. (Boise ID), Temperature-dependent DRAM refresh circuit.
  21. Casper Stephen L. (Boise ID) Loughmiller Daniel R. (Boise ID), Voltage compensating delay element.

이 특허를 인용한 특허 (87)

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  6. Telecco, Nicola, Data register with efficient erase, program verify, and direct bit-line memory access features.
  7. Drexler, Adrian J., Dual-phase delay-locked loop circuit and method.
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