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Fault resilient/fault tolerant computing 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-011/00
출원번호 US-0768437 (1996-12-18)
발명자 / 주소
  • Bissett Thomas Dale
  • Fiorentino Richard D.
  • Glorioso Robert M.
  • McCauley Diane T.
  • McCollum James D.
  • Tremblay Glenn A.
  • Troiani Mario
출원인 / 주소
  • Marathon Technologies Corporation
대리인 / 주소
    Fish & Richardson P.C.
인용정보 피인용 횟수 : 35  인용 특허 : 35

초록

Fault resilient or fault tolerant computers are produced by designating a first processor as a computing element, designating a second processor as a controller, connecting the computing element and the controller to produce a modular pair, and connecting at least two module pairs to produce a fault

대표청구항

[ What is claimed is:] [1.] A method of producing a fault resilient or fault tolerant computer, comprising:designating a first processor as a computing element;configuring the computing element to run an application program;designating a second processor as a controller;configuring the controller to

이 특허에 인용된 특허 (35)

  1. Vandling ; III Gilbert C. (Endicott NY), Asynchronous TMR processing system.
  2. Halpern Joseph Y. (Cupertino CA) Simons Barbara B. (Scotts Valley CA) Strong Hovey R. (San Jose CA), Centralized synchronization of clocks.
  3. Beal David G. (Longmont CO) Eifert Fred C. (Louisville CO) Ludlam Henry S. (Longmont CO) Milligan Charles A. (Golden CO) Rudeseal George A. (Boulder CO) Swiatek Paul R. (Lafayette CO), Data storage system for providing redundant copies of data on different disk drives.
  4. Long William L. (Pembroke MA) Wambach Robert F. (Attleboro MA) Baty Kurt F. (Medway MA) Lamb Joseph M. (Hopedale MA), Digital data processor with fault-tolerant peripheral interface.
  5. Yount Larry J. (Scottsdale AZ), Digital fail operational automatic flight control system utilizing redundant dissimilar data processing.
  6. McDonald John C. (Los Gatos CA) Baichtal James R. (Los Altos CA), Double redundant processor.
  7. Bruckert William F. (Northboro MA) Bissett Thomas D. (Derry NH), Dual rail processors with error checking on I/O reads.
  8. Bruckert William F. (Northboro MA) Bissett Thomas D. (Derry NH), Dual zone, fault tolerant computer system with error checking in I/O writes.
  9. Bruckert William F. (Northboro MA) Bissett Thomas D. (Derry NH) Riegelhaupt Norbert H. (Framingham MA), Dual-rail processor with error checking at single rail interfaces.
  10. Binkley Joseph H. (Palo Alto CA) Caro Perry A. (Palo Alto CA) Dillon John B. (Palo Alto CA) Fay Charles R. (Long Beach CA) Gibbons Jonathan (Mountain View CA) Hooks Hilary N. (Newark CA) Kadifa Abdo , Emulation with display update trapping.
  11. Julich Paul M. (Indialantic FL) Pearce Jeffrey B. (Melbourne FL), Fault detection and redundancy management system.
  12. Herbermann Carl R. (Centerport NY), Fault tolerant interface station.
  13. Bruckert William F. (Northboro MA) Bissett Thomas D. (Derry NH) Mazur Dennis (Worcester MA) Munzer John (Brookline MA), Fault tolerant, synchronized twin computer system with error checking of I/O communication.
  14. Jewett Douglas E. (Austin TX) Bereiter Tom (Austin TX) Vetter Brian (Austin TX), Fault-tolerant computer system with /CONFIG filesystem.
  15. Jewett Douglas E. (Austin TX) Bereiter Tom (Austin TX) Vetter Brian (Austin TX) Banton Randall G. (Austin TX) Cutts ; Jr. Richard W. (Georgetown TX) Westbrook ; deceased Donald C. (late of Austin TX , Fault-tolerant computer system with online recovery and reintegration of redundant components.
  16. Cutts ; Jr. Richard W. (Georgetown) Norwood Peter C. (Austin) DeBacker Kenneth C. (Austin) Mehta Nikhil A. (Austin) Jewett Douglas E. (Austin) Allison John D. (Austin TX) Horst Robert W. (Champaign I, Fault-tolerant computer with three independently clocked processors asynchronously executing identical code that are syn.
  17. Whiteside Arliss E. (Royal Oak MI) Freedman Morris D. (Southfield MI) Rothschild Alexander M. (Ann Arbor MI) Tasar mr (Harvard MA), Fault-tolerant multi-computer system.
  18. Katzman James A. (San Jose CA) Bartlett Joel F. (Palo Alto CA) Bixler Richard M. (Sunnyvale CA) Davidow William H. (Atherton CA) Despotakis John A. (Pleasanton CA) Graziano Peter J. (Los Altos CA) Gr, Fault-tolerant multiprocessor system.
  19. Rubinson Barry L. (Colorado Springs CO) Gardner Edward A. (Colorado Springs CO) Grace William A. (Colorado Springs CO) Lary Richard F. (Colorado Springs CO) Keck Dale R. (Colorado Springs CO), Interface between a pair of processors, such as host and peripheral-controlling processors in data processing systems.
  20. Bruckert William F. (Northboro MA) Bissett Thomas D. (Derry NH) Norcross Mitchell O. (Framingham MA) Ward Kenneth A. (Marlboro MA), Interface of non-fault tolerant components to fault tolerant system.
  21. Bissett Thomas D. (Derry NH) Riegelhaupt Norbert H. (Framingham MA) Berkson Mitch (Brighton MA), Memory device with transfer of ECC signals on time division multiplexed bidirectional lines.
  22. Sodos Martin (San Jose CA), Method and apparatus for dynamic chaining of DMA operations without incurring race conditions.
  23. Rowett Kevin J. (Cupertino CA), Method and apparatus for fault tolerant connection of a computing system to local area networks.
  24. Horst Robert W. (Cupertino CA), Method and apparatus for synchronizing a plurality of processors.
  25. Daniel Hans-Georg (Munich DEX) Engelsmann Karel (Munich DEX) Eggers Harald (Vierkirchen DEX), Method for abnormal restart of a multiprocessor computer of a telecommunication switching system.
  26. Horst Robert W. (Champaign IL), Multiple-processor computer system with asynchronous execution of identical code streams.
  27. Baum Richard I. (Poughkeepsie NY) Brotman Charles H. (Poughkeepsie NY) Rymarczyk James W. (Poughkeepsie NY), Multiprocessing packet switching connection system having provision for error correction and recovery.
  28. Walter Chris J. (Columbia MD) Kiekhafer Roger M. (Lincoln NE) Finn Alan M. (Amston CT), Operations controller for a fault tolerant multiple node processing system.
  29. Irwin John W. (Georgetown TX), Processor I/O and interrupt filters allowing a co-processor to run software unknown to the main processor.
  30. Bishop Thomas P. (Aurora IL) Butvila Jonas (LaGrange IL) Fitch David J. (Naperville IL) Hansen Robert C. (Wheaton IL) Schmitt David A. (Glen Ellyn IL) Surratt Grover T. (West Chicago IL), Reconfigurable dual processor system.
  31. Peet ; Jr. Charles E. (Austin ; TX) Allison John D. (Austin ; TX) Debacker Kenneth C. (Austin ; TX) Horst Robert W. (Champaign IL), Refresh control for dynamic memory in multiple processor system.
  32. Murphy Richard D. (Monroe CT) Clelford Douglas H. (Shelton CT), Selective disablement in fail-operational, fail-safe multi-computer control system.
  33. McLaughlin Paul F. (Hatfield PA) Bristow Robert W. (Hatboro PA), Synchronizing slave processors through eavesdrop by one on periodic sync-verify messages directed to another followed by.
  34. Binkley Joseph H. (Palo Alto CA) Caro Perry A. (Palo Alto CA) Fay Charles R. (Long Beach CA) Lee Jeffery W. (Sunnyvale CA) Neely Everett T. (Montara CA) Thompson Geoffrey O. (Palo Alto CA) Vukkadala , System for managing data which is accessible by file address or disk address via a disk track map.
  35. Bailey Bruce W. (Cupertino CA), System for measuring program execution by replacing an executable instruction with interrupt causing instruction.

이 특허를 인용한 특허 (35)

  1. Griffin, Gerry; McLoughlin, Michael, Apparatus and method for two computing elements in a fault-tolerant server to execute instructions in lockstep.
  2. Long,Finbarr Denis; Ardini,Joseph; Kirkpatrick,Dana A.; O'Keeffe,Michael James, Apparatus and methods for fault-tolerant computing using a switching fabric.
  3. Hillman, Robert A.; Conrad, Mark Steven, Cache coherency during resynchronization of self-correcting computer.
  4. Podanoffsky, Michael, Computerized diagnostics and failure recovery.
  5. Sundaram,Padma; Chen,Yulei; D'Ambrosio,Joseph G., Control system and method for validating operation of the control system.
  6. Bissett Thomas D. ; Leveille Paul A. ; Muench Erik, Fault resilient/fault tolerant computing.
  7. Thomas D. Bissett ; Paul A. Leveille ; Erik Muench, Fault resilient/fault tolerant computing.
  8. Somers, Jeffrey S.; Huang, Wen-Yi; Tetreault, Mark D.; Wegner, Timothy M., Fault-tolerant computer system with voter delay buffer.
  9. Yamazaki,Shigeo; Aino,Shigeyuki, Fault-tolerant computer system, re-synchronization method thereof and re-synchronization program thereof.
  10. Suffin, A. Charles; Amato, Joseph S.; Joyce, Paul, Fault-tolerant maintenance bus architecture.
  11. Suffin, A. Charles, Fault-tolerant maintenance bus protocol and method for using the same.
  12. Chester, Arthur W.; Roberie, Terry G.; Timken, Hye Kyung C.; Ziebarth, Michael S., Gasoline sulfur reduction in fluid catalytic cracking.
  13. Chester, Arthur W.; Roberie, Terry G.; Timken, Hye Kyung C.; Ziebarth, Michael S., Gasoline sulfur reduction in fluid catalytic cracking.
  14. Chester, Arthur W.; Timken, Hye Kyung Cho; Roberie, Terry G.; Ziebarth, Michael S., Gasoline sulfur reduction in fluid catalytic cracking.
  15. Chester,Arthur W.; Timken,Hye Kyung Cho; Roberie,Terry G.; Ziebarth,Michael S., Gasoline sulfur reduction in fluid catalytic cracking.
  16. Suffin, A. Charles, Method and apparatus for deterministically booting a computer system having redundant components.
  17. Bernick,David L.; Bruckert,William F.; Garcia,David J.; Jardine,Robert L.; Klecka,James S.; Mehra,Pankaj; Smullen,James R., Method and system executing user programs on non-deterministic processors.
  18. Somers, Jeffrey S.; Tetreault, Mark D.; Wegner, Timothy M., Method and system for upgrading fault-tolerant systems.
  19. Del Vigna, Jr.,Paul; Jardine,Robert L., Method and system of aligning execution point of duplicate copies of a user program by copying memory stores.
  20. Del Vigna, Jr.,Paul; Jardine,Robert L., Method and system of aligning execution point of duplicate copies of a user program by exchanging information about instructions executed.
  21. Kondo, Thomas J.; Jardine, Robert L; Bruckert, William F.; Garcia, David J.; Klecka, James S.; Smullen, James R.; Sprouse, Jeff; Stott, Graham B., Method and system of copying memory from a source processor to a target processor by duplicating memory writes.
  22. Bernick,David L.; Bruckert,William F.; Garcia,David J.; Jardine,Robert L.; Mehra,Pankaj; Smullen,James R., Method and system of determining whether a user program has made a system level call.
  23. Bruckert, William F.; Garcia, David J.; Heynemann, Thomas A.; Klecka, James S.; Sprouse, Jeffrey A., Method and system of exchanging information between processors.
  24. Kuntzsch Claus,DEX ; Mayer Frank,DEX, Method for the monitoring of integrated circuits.
  25. Conrad, Mark Steven; Hillman, Robert A., Methods and apparatus for managing and controlling power consumption and heat generation in computer systems.
  26. Conrad, Mark Steven; Hillman, Robert A., Methods and apparatus for managing and controlling power consumption and heat generation in computer systems.
  27. Hotra, Jonathan Nicholas; Turner, Donald Eugene, Methods and systems for executing software applications using hardware abstraction.
  28. Hotra, Jonathan N., Methods and systems for preserving certified software through virtualization.
  29. Hillman, Robert A.; Conrad, Mark Steven, Self-correcting computer.
  30. Hillman,Robert Allen; Conrad,Mark Steven, Self-correcting computer.
  31. Malekpour, Mahyar R., Self-stabilizing byzantine-fault-tolerant clock synchronization system and method.
  32. Malekpour, Mahyar R., Self-stabilizing distributed symmetric-fault tolerant synchronization protocol.
  33. Nelvin, Robert E.; Tetreault, Mark D.; Alden, Andrew; Dolaty, Mohsen; Edwards, Jr., John W.; Kement, Michael W.; MacLeod, John R., System and method for operating a system with redundant peripheral bus controllers.
  34. Fiorentino, Richard D.; Kaman, Charles H.; Troiani, Mario; Muench, Erik, System for cross-host, multi-thread session alignment.
  35. Hillman, Robert; Williamson, Gale, System, method and apparatus for error correction in multi-processor systems.
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