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Apparatus and method for identifying the features and the origin of a computer microprocessor 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-009/22
출원번호 US-0023916 (1993-02-26)
발명자 / 주소
  • Dreyer Robert S.
  • Corwin William M.
  • Alpert Donald B.
  • Wang Tsu-Hua
  • Lau Daniel G.
  • Pollack Frederick J.
출원인 / 주소
  • Intel Corporation
대리인 / 주소
    Blakely, Sokoloff, Taylor & Zafman LLP
인용정보 피인용 횟수 : 12  인용 특허 : 21

초록

A multi-level identification apparatus and method for providing at least two types of identification information, including a first type for identifying the origin of a microprocessor and the number of levels of identification information available, and a second type for identifying a family, a mode

대표청구항

[ What is claimed is:] [1.] A non-inferential method for identifying an origin of a microprocessor, wherein the microprocessor implements the method comprising the steps of:a) reading an indicia of origin from a memory in the microprocessor in response to an ID instruction;b) storing the indicia of

이 특허에 인용된 특허 (21)

  1. Amirghodsi Siamak (Prairie View IL) Daneshbodi Farnoud (Prairie View IL), Adaptive natural language computer interface system.
  2. Sutton Arthur J. (Cold Spring NY), Alternate processor continuation of task of failed processor.
  3. Dreyer Robert S. (Sunnyvale CA) Alpert Donald B. (Santa Clara CA), Apparatus and method for identifying a computer microprocessor.
  4. Jessen Jay Alan (Santa Clara CA) Nagarajan Palanivelu (Campbell CA) Flynn Sean Ludlow (Cupertino CA) Schneider James Alan (San Jose CA), Apparatus for causing a computer system to respond to emulated user interaction in the absence of actual user interactio.
  5. Kim Donguk (Seoul KRX), Auto-switching device for CPU logic circuits.
  6. Parks Terry J. (Round Rock TX), Circuit for determining between a first or second type CPU at reset by examining upper M bits of initial memory referenc.
  7. Cepulis Darren J. (Houston TX), Computer memory management method utilizing segmentation and protection techniques.
  8. Rogers ; Jr. Harry R. (Spring TX) Landry John A. (Tomball TX) Izquierdo Javier F. (Houston TX), Daisy-chained serial shift register for determining configuration of removable circuit boards in a computer system.
  9. Kono Hiromi (Higashimatsuyama JPX), Data processing system adaptable to using equivalent integrated circuits.
  10. Beardsley Brent C. (Tucson AZ) Hefferon Eugene P. (Poughkeepsie NY) Lynch Kenneth R. (Rhinebeck NY) Schimke Stephen W. (Tucson AZ) Shipman ; Jr. Lloyd R. (San Jose CA) Wethington Susan M. (Tucson AZ), Device initiated partial system quiescing.
  11. Sullivan Daniel T. (Bolton MA) Kaman Charles H. (Newton Highlands MA) O\Loughlin James F. (Westford MA) Kapadia Jamshed R. (Waltham MA), Diagnostic apparatus in a data processing system.
  12. Karp Alan H. (Palo Alto CA), Hardware assist for protecting PC software.
  13. Suzuki Noriyuki (Tokyo JPX) Asai Hironobu (Tokyo JPX), In-circuit emulator.
  14. Durst ; Jr. Robert T. (212 Shelton Rd. Monroe CT 06468) Hunter Kevin D. (440 Allyndale Dr. Stratford CT 06497), Method and system for preventing unauthorized use of software.
  15. Crosswy William C. (Houston TX), Method for distinguishing between a 286-type central processing unit and a 386-type central processing unit.
  16. Sherer W. Paul (Sunnyvale CA) Connery Glenn W. (Sunnyvale CA) Emery Scott A. (San Jose CA), Method for optimizing software for any one of a plurality of variant architectures.
  17. Sherer W. Paul (Sunnyvale CA) Connery Glenn W. (Sunnyvale CA) Emery Scott A. (San Jose CA), Method for optimizing software for any one of a plurality of variant architectures.
  18. Kurihara Jun\ichi (Mitaka JPX) Hirosawa Toshio (Machida JPX) Shibamiya Minoru (Yokohama JPX), Network control system for dynamically switching a logical connection between an identified terminal device and an indic.
  19. Chuang Te-Chih (Miao-Lee City TWX) Liao Yunn-Hung (Taipei TWX) Wei Lung (Taichung TWX) Lee Yi-Hsien (Taipei TWX), Single socket upgradeable computer motherboard with automatic detection and socket reconfiguration for inserted CPU chip.
  20. Freidin Philip (Sunnyvale CA), Universal microprocessor interface circuit.
  21. King Edward C. (Fremont CA) Goeppel Anton (Burgau DEX), Work station architecture with selectable CPU.

이 특허를 인용한 특허 (12)

  1. Chheda,Sachin; Choksey,Dhruv, Automatic selection of firmware for a computer that allows a plurality of process types.
  2. Calhoon, Sean; Carr, J. Scott; Rodriguez, Tony F., Data processing systems and methods.
  3. Lee, Van Hoa; Tran, Kiet Anh, Identifying architecture and bit specification of processor implementation using bits in identification register.
  4. Montgomery, Wallace Paul; Lueck, Andrew; Strongin, Geoffrey S. S., Method and apparatus for making a processor sideband interface adhere to secure mode restrictions.
  5. Nalawadi,Rajeev K.; Siddiqi,Faraz A., Method and apparatus for modifying the contents of revision identification register.
  6. Parker Allan ; Skrovan Joseph C., Method for generating functional tests for a microprocessor having several operating modes and features.
  7. Montgomery, Wallace P.; Tobias, David F.; Clark, Michael T., Non-destructive sideband reading of processor state information.
  8. Hamersley,Richard Alan, Processing of processor performance state information.
  9. Suchy, Miroslav; Zazrivec, Milan, Provisioning a device with multiple bit-size versions of a software component.
  10. Suchy, Miroslav; Zazrivec, Milan, Provisioning a device with multiple bit-size versions of a software component.
  11. Suchy, Miroslav; Zazrivec, Milan, Registration process for determining compatibility with 32-bit or 64-bit software.
  12. Doudoumopolous,Nicholas, Self-identifying integrated circuits and method for fabrication thereof.
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