초록 ▼

A FET package including one or more FETs includes an arrangement of three metallization layers for the gate, drain, and source terminals thereof. The layers include a gate runner metallizaton layer that allows the FETs to be arranged in a parallel manner so as to reduce the overall total on-state re

A FET package including one or more FETs includes an arrangement of three metallization layers for the gate, drain, and source terminals thereof. The layers include a gate runner metallizaton layer that allows the FETs to be arranged in a parallel manner so as to reduce the overall total on-state resistance to an optimum value, while allowing the gate switching capacitance to be increased to an optimized value. The gate runner metallization layer is arranged to minimize the overlapping capacitance between the gate and source terminals and between the gate and drain terminals. Additional semiconductor devices may be incorporated into the FET package using additional terminals interconnected through the metallization layers, thus providing additional functions.

대표청구항 ▼

[ What is claimed is:] [1.] A field-effect transistor (FET) package comprising one or more FETs, each FET having gate, source, and drain terminals, each gate terminal having a resistance, the drain and source terminals of each FET having an overlapping capacitance relative to the gate terminal, the

[ What is claimed is:] [1.] A field-effect transistor (FET) package comprising one or more FETs, each FET having gate, source, and drain terminals, each gate terminal having a resistance, the drain and source terminals of each FET having an overlapping capacitance relative to the gate terminal, the FET package comprising:a first layer of metallization on which each of the one or more FETs is affixed, the first layer being electrically interconnected to the drain terminal of each of the one or more FETs;a second layer of metallization arranged in parallel with the first layer, the second layer being electrically interconnected to the source terminal of each of the one or more FETs; anda third layer of metallization comprising a gate runner and being electrically interconnected to the gate terminal of each of the one or more FETs, the gate runner arranged in parallel with the first layer and the second layer and having a portion overlapping the first layer and the second layer to minimize the effective resistance of the gate terminals and to minimize the overlapping capacitance between the drain and gate terminals and between the source and gate terminals.