$\require{mediawiki-texvc}$
  • 검색어에 아래의 연산자를 사용하시면 더 정확한 검색결과를 얻을 수 있습니다.
  • 검색연산자
검색연산자 기능 검색시 예
() 우선순위가 가장 높은 연산자 예1) (나노 (기계 | machine))
공백 두 개의 검색어(식)을 모두 포함하고 있는 문서 검색 예1) (나노 기계)
예2) 나노 장영실
| 두 개의 검색어(식) 중 하나 이상 포함하고 있는 문서 검색 예1) (줄기세포 | 면역)
예2) 줄기세포 | 장영실
! NOT 이후에 있는 검색어가 포함된 문서는 제외 예1) (황금 !백금)
예2) !image
* 검색어의 *란에 0개 이상의 임의의 문자가 포함된 문서 검색 예) semi*
"" 따옴표 내의 구문과 완전히 일치하는 문서만 검색 예) "Transform and Quantization"

과학기술 지식인프라 ScienceON

상세검색 다국어 입력
도움말도움말

특허 상세정보

MyON담기
내보내기

Programmable logic device including configuration data or user data memory slices

국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판) G11C-013/00   
미국특허분류(USC) 365/182 ; 365/051 ; 365/063
출원번호 US-0001156 (1997-12-30)
발명자 / 주소
출원인 / 주소
대리인 / 주소
    Harms
인용정보 피인용 횟수 : 71  인용 특허 : 36
초록
▼

A programmable logic device (PLD) comprises at least one configurable element, and a plurality of programmable logic elements for configuring the configurable element(s). Alternatively, a PLD comprises an interconnect structure and a plurality of programmable logic elements for configuring the interconnect structure. In either embodiment, at least one of the programmable logic elements includes N memory cells. A predetermined one of the N memory cells forms part of a memory slice, wherein at least a portion of each slice of the programmable logic device ...

대표
청구항
▼

[ We claim:] [1.] A programmable logic device comprising:at least one configurable element;a plurality of programmable logic elements for configuring said at least one configurable element, wherein at least one of said programmable logic elements includes N memory cells, wherein a predetermined one of said N memory cells for said plurality of programmable logic elements forms part of a memory slice, wherein one memory slice provides one configuration of said programmable logic device, and wherein at least a portion of each slice of said programmable logi...

이 특허에 인용된 특허 (36)

  1. Hsieh Hung-Cheng (San Jose CA). 5-Transistor memory cell which can be reliably read and written. USP1988064750155.
  2. Hsieh Hung-Cheng (Sunnyvale CA). 5-transistor memory cell with known state on power-up. USP1989044821233.
  3. Parlour David B. (Pittsburgh PA) Goetting F. Erich (Cupertino CA) Trimberger Stephen M. (San Jose CA). Adaptive programming method for antifuse technology. USP1994095349248.
  4. Hsieh Wen-Jai (Vancouver WA) Jenq Yih-Chyun (Lake Oswego OR) Horng Chi-Song (Palo Alto CA). Apparatus for flexibly routing signals between pins of electronic devices. USP1995065426738.
  5. Bieber Larry C. (Simi Valley CA) Woodell Jack L. (La Canada CA). Apparatus for generating telex signaling sequences in a distributed processing telex exchange. USP1981094288658.
  6. Agrawal Om P. (San Jose CA) Wright Michael J. (Menlo Park CA) Shen Ju (San Jose CA). Array of configurable logic blocks each including a first lookup table output coupled to selectively replace an output o. USP1995115469368.
  7. Trimberger Stephen M. (San Jose CA). Computer-implemented method of optimizing a design in a time multiplexed programmable logic device. USP1997125701441.
  8. Trimberger Stephen M. (San Jose CA) Carberry Richard A. (Los Gatos CA) Johnson Robert A. (San Jose CA) Wong Jennifer (Fremont CA). Configuration modes for a time multiplexed programmable logic device. USP1997025600263.
  9. Zeilenga Jack H. (San Francisco CA) Hoenninger ; III John (Oakland CA). Continually loadable microcode store for MRI control sequencers. USP1992095144242.
  10. Drerup Bernard C. (Austin TX) Peterson James C. (Austin TX). Converting a central arbiter to a slave arbiter for interconnected systems. USP1994125377331.
  11. Takahashi Etsuo (Tokyo JPX). LSI logic synthesis device and method therefor. USP1996065530654.
  12. Chene Mon R. (Cupertino CA) Trimberger Stephen M. (San Jose CA). Logic placement using positionally asymmetrical partitioning algorithm. USP1993065224056.
  13. Trimberger Stephen M. (San Jose CA) Chene Mon-Ren (Cupertino CA). Logic placement using positionally asymmetrical partitioning method. USP1996045513124.
  14. Dingwall Andrew G. F. (Bridgewater NJ). Memory organization. USP1980024189782.
  15. Dangelo Carlos (Los Gatos CA) Deeley Richard (San Jose CA) Nagasamy Vijay (Union City CA) Vafai Manoucher (Los Gatos CA). Method and system for creating and validating low level description of electronic design from higher level, behavior-ori. USP1996095553002.
  16. Pickett Scott K. (San Jose CA) Luich Thomas M. (Campbell CA) Swift ; IV Arthur L. (Welches OR). Method for operating a multiple page programmable logic device. USP1992015081375.
  17. Trimberger Stephen M. (San Jose CA). Method for programming an FPLD using a library-based technology mapping algorithm. USP1996055521835.
  18. Trimberger Stephen M. (San Jose CA) Carberry Richard A. (Los Gatos CA) Johnson Robert A. (San Jose CA) Wong Jennifer (Fremont CA). Method of time multiplexing a programmable logic device. USP1997055629637.
  19. Veneski Gerard A. (Boca Raton FL). Microprocessor control system utilizing overlapped programmable logic arrays. USP1987044661901.
  20. Puhl Larry C. (Sleepy Hollow IL). Microprocessor with duplicate registers for processing interrupts. USP1984024434461.
  21. Moore Victor S. (Pompano Beach FL) Veneski Gerard A. (Boca Raton FL) Parker Tony E. (Boca Raton FL) Rhodes ; Jr. Joseph C. (Boca Raton FL) Kraft Wayne R. (Coral Springs FL) Stahl ; Jr. William L. (Co. Microword control system utilizing multiplexed programmable logic arrays. USP1986064594661.
  22. Hickman Patrick T. (Chandler AZ) Schucker Douglas W. (Mesa AZ) Tou Jarvis (Gilbert AZ). Programmable block architected heterogeneous integrated circuit. USP1992105155390.
  23. Agrawal Om P. (San Jose CA) Wright Michael J. (Boulder CO). Programmable gate array with logic cells having configurable output enable. USP1993025185706.
  24. Furtek Frederick C. (Arlington MA). Programmable logic cell and array. USP1992105155389.
  25. Ong Randy T. (Cupertino CA). Programmable logic device which stores more than one configuration and means for switching configurations. USP1995065426378.
  26. Agrawal Om (San Jose CA) Shankar Kapil (San Jose CA). Programmable logic device with subroutine stack and random access memory. USP1991085042004.
  27. Lee Sai-keung (Milpitas CA). Programmable power supply level detection and initialization circuitry. USP1991055019996.
  28. Deglin Rene′ (Velizy-Villacoublay FRX) Reymond Gilbert (Malakoff FRX). Programmable sequential logic. USP1980124237545.
  29. Eng Robert C. (Boca Raton FL) Galella John W. (Boca Raton FL) McCrary Rex E. (Boca Raton FL) McDonald Mark G. (Delray Beach FL) Stelzer Eric H. (Boca Raton FL) Yentz Frederick C. (Boca Raton FL). Providing alternate bus master with multiple cycles of bursting access to local bus in a dual bus system including a pro. USP1995115469577.
  30. Crafts Harold S. (Colorado Springs CO) McKinley William W. (Fort Collins CO). Repeatedly programmable logic array using dynamic access memory. USP1995075432388.
  31. Cox William D. (San Jose CA) Lehmann Eric E. (San Francisco CA) Lulla Mukesh T. (Santa Clara CA) Nathamuni Venkatesh R. (San Jose CA). Select set-based technology mapping method and apparatus. USP1996065526276.
  32. Trimberger Stephen M. (San Jose CA) Carberry Richard A. (Los Gatos CA) Johnson Robert A. (San Jose CA) Wong Jennifer (Fremont CA). Sequencer for a time multiplexed programmable logic device. USP1996125583450.
  33. Sawase Terumi (Hanno JPX) Hagiwara Yoshimune (Hachioji JPX) Nakamura Hideo (Tokyo JPX) Hatori Hiroyuki (Takasaki JPX) Baba Shirou (Tokorozawa JPX) Akao Yasushi (Kokubunji JPX). Single chip microprocessor for satisfying requirement specification of users. USP1995065426744.
  34. Trimberger Stephen M. (San Jose CA) Carberry Richard A. (Los Gatos CA) Johnson Robert Anders (San Jose CA) Wong Jennifer (Fremont CA). Time multiplexed programmable logic device. USP1997075646545.
  35. Kajimura Hiroshi (Tokyo JPX) Kouchi Toshihito (Tama JPX) Toda Akitoshi (Kunitachi JPX) Isono Yasuo (Fussa JPX) Mimura Yoshiyuki (Hachioji JPX) Ohta Hiroko (Hachioji JPX) Shimizu Ryouhei (Koshigaya JP. Tunnel current data storage apparatus having separate lever bodies. USP1991105053995.
  36. Furtek Frederick C. (Menlo Park CA) Camarota Rafael C. (San Jose CA). Versatile programmable logic cell for use in configurable logic arrays. USP1993095245227.

이 특허를 인용한 특허 피인용횟수: 71

  1. Ramchandran, Amit. Adaptable datapath for a digital processing system. USP2013028380884.
  2. Ramchandran, Amit. Adaptable datapath for a digital processing system. USP2015049015352.
  3. Ramchandran, Amit. Adaptable datapath for a digital processing system. USP2014048706916.
  4. Ramchandran, Amit. Adaptable datapath for a digital processing system. USP2009107606943.
  5. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J.. Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements. USP2015109164952.
  6. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J.. Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements. USP2013098543795.
  7. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James. Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements. USP2013098533431.
  8. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James. Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements. USP2004126836839.
  9. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James. Adaptive integrated circuitry with heterogenous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements. USP2013098543794.
  10. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James. Adaptive processor for performing an operation with simple and complex units each comprising configurably interconnected heterogeneous elements. USP2013018356161.
  11. Heidari-Bateni, Ghobad; Plunkett, Robert Thomas. Adaptive, multimode rake receiver for dynamic search and multipath reception. USP2003096618434.
  12. Master, Paul L.; Uvacek, Bohumir. Apparatus and method for adaptive multimedia reception and transmission in communication environments. USP2015049002998.
  13. Master, Paul L.; Watson, John. Apparatus, method and system for generating a unique hardware adaptation inseparable from correspondingly unique content. USP2005116968454.
  14. Master, Paul L.; Smith, Stephen J.; Watson, John. Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements. USP2016059330058.
  15. Master, Paul L.; Smith, Stephen J.; Watson, John. Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements. USP2014118880849.
  16. Master, Paul L.; Smith, Stephen J.; Watson, John. Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements. USP2012088250339.
  17. Master,Paul L.; Smith,Stephen J.; Watson,John. Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements. USP2006016986021.
  18. Master, Paul L.; Smith, Stephen J.; Watson, John. Apparatus, system and method for configuration of adaptive integrated circuitry having fixed, application specific computational elements. USP2017039594723.
  19. Master, Paul L.; Smith, Stephen J.; Watson, John. Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements. USP2012078225073.
  20. Hogenauer, Eugene B.. Arithmetic node including general digital signal processing functions for an adaptive computing machine. USP2015028949576.
  21. Howard, Ric; Katragadda, Ramana V.. Asynchronous, independent and multiple process shared memory system in an adaptive computing architecture. USP2009087577799.
  22. de Waal, Abraham B.; Diard, Franck R.. Automatic quality testing of multimedia rendering by software drivers. USP2011077987065.
  23. Nagpal, Sumit; Maguluri, Sreevidya; Kumar, Prashanth. Circuit design with predefined configuration of parameterized cores. USP2015119183337.
  24. Sood, Santosh Kumar. Circuits for and methods of providing voltage level shifting in an integrated circuit device. USP2016059337841.
  25. Heidari, Ghobad; Chang, Kuor Hsin; Master, Paul L.; Hogenauer, Eugene B.; Scheuermann, Walter James. Communications module, device, and method for implementing a system acquisition function. USP2009117620097.
  26. Master, Paul L.; Watson, John. Configurable hardware based digital imaging apparatus. USP2009107609297.
  27. Rubin, Owen Robert; Murray, Eric; Uhrig, Nalini Praba. Consumer product distribution in the embedded system market. USP2010017644279.
  28. Scheuermann, W. James; Hogenauer, Eugene B.. Control node for multi-core system. USP20190110185502.
  29. Furtek, Frederick Curtis; Master, Paul L.. External memory controller. USP2012098266388.
  30. Furtek, Frederick Curtis; Master, Paul L.. External memory controller node. USP2014078769214.
  31. Furtek, Fredrick Curtis; Master, Paul L.. External memory controller node. USP2011077984247.
  32. Furtek, Fredrick Curtis; Master, Paul L.. External memory controller node. USP2011077979646.
  33. Scheuermann,Walter James. Hardware implementation of the secure hash standard. USP2009027489779.
  34. Scheuermann, W. James; Hogenauer, Eugene B.. Hardware task manager. USP2017059665397.
  35. Scheuermann, W. James; Hogenauer, Eugene B.. Hardware task manager. USP2012068200799.
  36. Scheuermann, W. James; Hogenauer, Eugene B.. Hardware task manager. USP2010017653710.
  37. Scheuermann, W. James; Hogenauer, Eugene B.. Hardware task manager. USP2014078782196.
  38. Master,Paul L.; Hogenauer,Eugene; Scheuermann,Walter James. Hierarchical interconnect for configuring separate interconnects for each group of fixed and diverse computational elements. USP2008017325123.
  39. Furtek, Frederick Curtis; Master, Paul L.; Plunkett, Robert Thomas. Input/output controller node in an adaptable computing environment. USP2009117624204.
  40. Heidari-Bateni, Ghobad; Sambhwani, Sharad D.. Internal synchronization control for adaptive integrated circuitry. USP2012108296764.
  41. Sambhwani, Sharad; Heidari, Ghobad. Low I/O bandwidth method and system for implementing detection and identification of scrambling codes. USP2013058442096.
  42. Sambhwani, Sharad; Heidari, Ghobad. Low I/O bandwidth method and system for implementing detection and identification of scrambling codes. USP2010027668229.
  43. Sambhwani,Sharad; Heidari,Ghobad. Low I/O bandwidth method and system for implementing detection and identification of scrambling codes. USP2009037512173.
  44. Teig, Steven; Hetzel, Asmus. Method and apparatus for pre-tabulating sub-networks. USP2012048151227.
  45. Musselman, Roy Glenn. Method and apparatus to use clock bursting to minimize command latency in a logic simulation hardware emulator / accelerator. USP2010057716036.
  46. Master, Paul L.. Method and system for achieving individualized protected space in an operating system. USP2010027660984.
  47. Master, Paul L.. Method and system for creating and programming an adaptive computing engine. USP2011017865847.
  48. Merchant, James Daniel; Carskadon, Gordon; Evans, Brian P.; Hunt, Jeffery Scott; Nayak, Anup; Wright, Andrew. Method and system for generating a bit order data structure of configuration bits from a schematic hierarchy. USP2005066904436.
  49. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L.. Method and system for managing hardware resources to implement system functions using an adaptive computing architecture. USP2015059037834.
  50. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L.. Method and system for managing hardware resources to implement system functions using an adaptive computing architecture. USP2016079396161.
  51. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L.. Method and system for managing hardware resources to implement system functions using an adaptive computing architecture. USP2013118589660.
  52. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L.. Method and system for managing hardware resources to implement system functions using an adaptive computing architecture. USP2010077752419.
  53. Scheuermann, W. James. Method and system for reconfigurable channel coding. USP2014078767804.
  54. Scheuermann, W. James. Method and system for reconfigurable channel coding. USP2012088249135.
  55. Scheuermann, W. James. Method and system for reconfigurable channel coding. USP2010107809050.
  56. Scheuermann, W. James. Method and system for reconfigurable channel coding. USP2010107822109.
  57. Master, Paul L.; Scheuermann, W. James. Method and system for reducing the time-to-market concerns for embedded system design. USP2009117620678.
  58. Schiefele, Walter P.; Krueger, Robert O.. Method for creating circuit redundancy in programmable logic devices. USP2003026526559.
  59. Master,Paul L.; Hogenauer,Eugene; Wu,Bicheng William; Chuang,Dan MingLun; Freeman Benson,Bjorn. Method, system and program for developing and scheduling adaptive integrated circuity and corresponding control or configuration information. USP2009017478031.
  60. Karp, James; Hart, Michael J.. Operating a programmable integrated circuit with functionally equivalent configuration bitstreams. USP2013088519741.
  61. Akaogi Takao ; Kurihara Kazuhiro ; Chen Tien-Min. Output multiplexing implementation for a simultaneous operation flash memory device. USP2000096118698.
  62. Scheuermann,W. James. Processing architecture for a reconfigurable arithmetic node. USP2008107433909.
  63. Master, Paul L.. Profiling of software and circuit designs utilizing data operation analyses. USP2012098276135.
  64. Trimberger, Stephen M.. Programmable interconnect element and method of implementing a programmable interconnect element. USP2013098536896.
  65. Master, Paul L.; Murray, Eric; Mehegan, Joseph; Plunkett, Robert Thomas. Secure storage of program code for an embedded system. USP2010097802108.
  66. Master,Paul L.; Watson,John. Storage and delivery of device features. USP2009027493375.
  67. Jacob,Rojit; Chuang,Dan Minglun. System and method using embedded microprocessor as a node in an adaptable computing machine. USP2009037502915.
  68. Master, Paul L.; Watson, John. System for adapting device standards after manufacture. USP2009107602740.
  69. Master, Paul L.; Watson, John. System for authorizing functionality in adaptable hardware devices. USP201109E042743.
  70. Katragadda, Ramana; Spoltore, Paul; Howard, Ric. Task definition for specifying resource requirements. USP2012018108656.
  71. Tuan, Tim. Time-multiplexed, asynchronous device. USP2016059355690.

IPC 상위 출원인