초록 ▼

A programmable logic device (PLD) comprises at least one configurable element, and a plurality of programmable logic elements for configuring the configurable element(s). Alternatively, a PLD comprises an interconnect structure and a plurality of programmable logic elements for configuring the inter

A programmable logic device (PLD) comprises at least one configurable element, and a plurality of programmable logic elements for configuring the configurable element(s). Alternatively, a PLD comprises an interconnect structure and a plurality of programmable logic elements for configuring the interconnect structure. In either embodiment, at least one of the programmable logic elements includes N memory cells. A predetermined one of the N memory cells forms part of a memory slice, wherein at least a portion of each slice of the programmable logic device is allocated to either configuration data or user data memory. Typically, one memory slice provides one configuration of the programmable logic device. In accordance with one embodiment, a memory access port is coupled between at least one of the N memory cells and either one configurable element or the interconnect, thereby facilitating loading of new configuration data into other memory slices during the one configuration. The new configuration data may include off-chip or on-chip data. The present invention typically allocates at least one slice to user data memory and includes means for disabling access to at least one of the N memory cells.

대표청구항 ▼

[ We claim:] [1.] A programmable logic device comprising:at least one configurable element;a plurality of programmable logic elements for configuring said at least one configurable element, wherein at least one of said programmable logic elements includes N memory cells, wherein a predetermined one

[ We claim:] [1.] A programmable logic device comprising:at least one configurable element;a plurality of programmable logic elements for configuring said at least one configurable element, wherein at least one of said programmable logic elements includes N memory cells, wherein a predetermined one of said N memory cells for said plurality of programmable logic elements forms part of a memory slice, wherein one memory slice provides one configuration of said programmable logic device, and wherein at least a portion of each slice of said programmable logic device is allocated to either configuration data or user data memory; andmeans for loading new user data into other memory slices during said one configuration.