초록 ▼

A low power scannable asynchronous counter which is fully testable and which consumes low power in a functional mode consists of counter cells cascaded through NOR gate circuits to which clock signals are applied for each of the stages or cells. Each of the stages or cells comprises a flip-flop and

A low power scannable asynchronous counter which is fully testable and which consumes low power in a functional mode consists of counter cells cascaded through NOR gate circuits to which clock signals are applied for each of the stages or cells. Each of the stages or cells comprises a flip-flop and a multiplexer which together operate as a toggle flip-flop only when all of the previous flip-flops are set. The result is that the flip-flop clock is forced high preventing any transition of the flip-flop internal clock tree for all stages or cells where the output is low. Thus, no power consumption of such stages takes place during functional operation. In the scan test mode, the counter operates as a shift register and it is fully testable.

대표청구항 ▼

[ What is claimed is:] [1.] A low power scannable asynchronous counter including in combination:a source of clock signals;a source of scan data input signals;a source of scan mode signals;a head cell having (a)a first flip-flop with normal and inverted outputs, a clock input, and a data input, and (

[ What is claimed is:] [1.] A low power scannable asynchronous counter including in combination:a source of clock signals;a source of scan data input signals;a source of scan mode signals;a head cell having (a)a first flip-flop with normal and inverted outputs, a clock input, and a data input, and (b) a first multiplexer with an output coupled to the data input of said first flip-flop, a first input coupled with the inverted output of said first flip-flop, a second input coupled with said source of scan data input signals, and a selector input coupled with said source of scan mode signals;at least one intermediate cell having (a) a second flip-flop with normal and inverted outputs, a clock input, and a data input, and (b) a second multiplexer with an output coupled to the data input of said second flip-flop, a first input coupled with the inverted output of said second flip-flop, a second input coupled with the normal output of said first flip-flop, and a selector input coupled with said source of scan mode signals; and (c) a first gate circuit with a first input coupled with said source of scan mode signals, a second input coupled with the inverted normal output of said first flip-flop, a third input coupled with said source of clock signals, and an output coupled to the clock input of said second flip-flop.