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Process for making a chip sized semiconductor device 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/44
출원번호 US-0040370 (1998-03-18)
우선권정보 JP-0259861 (1995-10-06)
발명자 / 주소
  • Akagawa Masatoshi,JPX
  • Higashi Mitsutoshi,JPX
  • Iizuka Hajime,JPX
  • Arai Takehiko,JPX
출원인 / 주소
  • Shinko Electric Industries Co. Ltd., JPX
대리인 / 주소
    Staas & Halsey
인용정보 피인용 횟수 : 55  인용 특허 : 13

초록

A process for making a chip sized semiconductor device, in which a semiconductor chip is prepared so as to have electrodes on one of surfaces thereof and an electrically insulating passivation film formed on the one surface except for areas where the electrodes exist. An insulation sheet is prepared

대표청구항

[ We claim:] [1.] A process for making a chip sized semiconductor device, said process comprising:preparing a wafer from which a plurality of semiconductor chips are made, each of said semiconductor chips having electrodes on a surface thereof and an electrically insulating passivation film formed o

이 특허에 인용된 특허 (13)

  1. Akagawa Masatoshi (Nagano JPX), Chip sized semiconductor device.
  2. Takada Norimasa (Tokyo JPX), Flip chip type semiconductor device.
  3. Berg Howard M. ; Ganesan Sankaranarayanan ; Lewis Gary L. ; Hawkins George W. ; Sloan James W. ; Bolton Scott C., Method for making a moisture resistant semiconductor device having an organic substrate.
  4. Shirahata Hisashi (Kanagawa JPX), Method of fabricating a bump electrode for an integrated circuit device.
  5. Barber Ivor G., Method of flip chip assembly.
  6. Matloubian Mehran (Encino CA) Macdonald Perry A. (Culver City CA) Rensch David B. (Thousand Oaks CA) Larson Lawrence E. (Bethesda MD), Microwave/millimeter wave circuit structure with discrete flip-chip mounted elements, and method of fabricating the same.
  7. Bureau Jean-Marc (Palaiseau FRX) Bernard Francois (Les Ulis FRX) Broussoux Dominique (Marcoussis FRX) Vergnolle Claude (Limours FRX), Process for manufacturing a multilayer integrated circuit interconnection.
  8. Yasunaga Masatoshi (Hyogo JPX) Nakao Shin (Hyogo JPX) Baba Shinji (Hyogo JPX) Matsuo Mitsuyasu (Hyogo JPX) Matsushima Hironori (Hyogo JPX), Resin seal semiconductor package.
  9. Chikaki Shinichi (Tokyo JPX), Semiconductor device.
  10. Hosomi Eiichi (Kawasaki JPX) Takubo Chiaki (Yokohama JPX) Tazawa Hiroshi (Ichikawa JPX) Miyamoto Ryouichi (Kawasaki JPX) Arai Takashi (Oita JPX) Shibasaki Koji (Kawasaki JPX), Semiconductor device comprising fine bump electrode having small side etch portion and stable characteristics.
  11. Mori Katsunobu (Nara JPX), Semiconductor device having external electrodes formed in concave portions of an anisotropic conductive film.
  12. Oku Kazutoshi (Hyogo JPX) Hirosue Masahiro (Hyogo JPX), Semiconductor device with an elevated bonding pad.
  13. Johnson Eric Arthur, Thermally enhanced flip chip package and method of forming.

이 특허를 인용한 특허 (55)

  1. Huang,Min Lung; Tsai,Chi Long; Weng,Chao Fu; Su,Ching Huei, Chip packaging structure having redistribution layer with recess.
  2. Lee, Jin-Yuan; Lin, Mou-Shiung; Huang, Ching-Cheng, Chip structure and process for forming the same.
  3. Lee, Jin-Yuan; Lin, Mou-Shiung; Huang, Ching-Cheng, Chip structure and process for forming the same.
  4. Lee,Jin Yuan; Lin,Mou Shiung; Huang,Ching Cheng, Chip structure and process for forming the same.
  5. Lin,Mou Shiung; Lee,Jin Yuan; Huang,Ching Cheng, Chip structure and process for forming the same.
  6. Lin,Mou Shiung; Lee,Jin Yuan; Huang,Ching Cheng, Chip structure and process for forming the same.
  7. Hashimoto, Nobuaki, Electronic board, method of manufacturing the same, and electronic device.
  8. Hashimoto, Nobuaki, Electronic board, method of manufacturing the same, and electronic device.
  9. Hashimoto, Nobuaki, Electronic board, method of manufacturing the same, and electronic device.
  10. Hashimoto, Nobuaki, Electronic component and semiconductor device, method of making the same and method of mounting the same, circuit board and electronic instrument.
  11. Hashimoto, Nobuaki, Electronic component and semiconductor device, method of making the same and method of mounting the same, circuit board, and electronic instrument.
  12. Hashimoto, Nobuaki, Electronic component and semiconductor device, method of making the same and method of mounting the same, circuit board, and electronic instrument.
  13. Hashimoto,Nobuaki, Electronic component and semiconductor device, method of making the same and method of mounting the same, circuit board, and electronic instrument.
  14. Hashimoto,Nobuaki, Electronic component and semiconductor device, method of making the same and method of mounting the same, circuit board, and electronic instrument.
  15. Hashimoto,Nobuaki, Electronic component and semiconductor device, method of making the same and method of mounting the same, circuit board, and electronic instrument.
  16. Nobuaki Hashimoto JP, Electronic component and semiconductor device, method of making the same and method of mounting the same, circuit board, and electronic instrument.
  17. Hashimoto, Nobuaki, Electronic component, semiconductor device, methods of manufacturing the same, circuit board, and electronic instrument.
  18. Hashimoto, Nobuaki, Electronic component, semiconductor device, methods of manufacturing the same, circuit board, and electronic instrument.
  19. Hashimoto, Nobuaki, Electronic component, semiconductor device, methods of manufacturing the same, circuit board, and electronic instrument.
  20. Hashimoto,Nobuaki, Electronic component, semiconductor device, methods of manufacturing the same, circuit board, and electronic instrument.
  21. Michael Zafrany FR; Philippe Patrice FR, Electronic module for chip card.
  22. Zafrany, Michael; Patrice, Philippe, Electronic module for chip card.
  23. Sunohara,Masahiro; Murayama,Kei; Mashino,Naohiro; Higashi,Mitsutoshi, Electronic parts packaging structure and method of manufacturing the same.
  24. Wen Ying-Nan,TWX ; Kung Ling-Chen,TWX ; Lu Szu-Wei,TWX ; Uang Ruoh-Huey,TWX, Method for forming fine-pitched solder bumps.
  25. Towle,Steven; Jones,Martha; Vu,Quat T., Method for packaging a microelectronic device using on-die bond pad expansion.
  26. Saitou Nobukatsu,JPX, Method of forming projection electrodes.
  27. Hashimoto, Nobuaki, Method of making electronic device.
  28. Kiyonori Watanabe JP, Method of manufacturing a bump electrode semiconductor device using photosensitive resin.
  29. Oi,Kiyoshi; Shimizu,Noriyoshi; Horikawa,Yasuyoshi, Method of manufacturing electronic part packaging structure.
  30. Machida, Yoshihiro, Method of manufacturing semiconductor device.
  31. Honda,Hirokazu, Multilayer interconnection board, semiconductor device having the same, and method of forming the same as well as method of mounting the semiconductor chip on the interconnection board.
  32. Honda, Hirokazu, Multilayer interconnection board, semiconductor device having the same, and method of forming the same as well as method of mounting the semicondutor chip on the interconnection board.
  33. Witzman Sorin,CAX ; Tencer Elizabeth M.,CAX ; Tencer Michal S.,CAX ; Davies William T.,CAX ; Kubin Richard S.,CAX, Process of assembling an integrated circuit and a terminal substrate using solder reflow and adhesive cure.
  34. Song, Young Hee; Choi, Il Heung; Kim, Jeong Jin; Sohn, Hae Jeong; Lee, Chung Woo, Semiconductor chip having bond pads.
  35. Song, Young Hee; Choi, Il Heung; Kim, Jeong Jin; Sohn, Hae Jeong; Lee, Chung Woo, Semiconductor chip having bond pads.
  36. Song, Young-Hee; Choi, Il-Heung; Kim, Jeong-Jin; Sohn, Hae-Jeong; Lee, Chung-Woo, Semiconductor chip having bond pads.
  37. Song,Young Hee; Choi,Il Heung; Kim,Jeong Jin; Sohn,Hae Jeong; Lee,Chung Woo, Semiconductor chip having bond pads.
  38. Song, Young Hee; Choi, Il Heung; Kim, Jeong Jin; Sohn, Hae Jeong; Lee, Chung Woo, Semiconductor chip having bond pads and multi-chip package.
  39. Tomofumi Nakamura JP, Semiconductor chip or device having a connecting member formed on a surface protective film.
  40. Atsushi Kazama JP; Akihiro Yaguchi JP; Hideo Miura JP, Semiconductor device.
  41. Shinkai, Hiroyuki; Okumura, Hiroshi, Semiconductor device.
  42. Kikuchi, Hidekazu, Semiconductor device and method for manufacturing.
  43. Strothmann, Thomas J.; Yoon, Seung Wook; Lin, Yaojian, Semiconductor device and method of forming encapsulated wafer level chip scale package (EWLCSP).
  44. Kasai, Masaki; Okumura, Hiroshi, Semiconductor device bonding with stress relief connection pads.
  45. Kasai, Masaki; Okumura, Hiroshi, Semiconductor device bonding with stress relief connection pads.
  46. Shinkai, Hiroyuki; Okumura, Hiroshi, Semiconductor device employing wafer level chip size package technology.
  47. Aiba, Yoshitaka; Sato, Mitsutaka, Semiconductor device manufacturing method having a step of applying a copper foil on a substrate as a part of a wiring connecting an electrode pad to a mounting terminal.
  48. Hiroyuki Nakanishi JP; Katsunobu Mori JP; Toshiya Ishio JP; Shinji Suminoe JP, Semiconductor integrated circuit device and manufacturing method thereof.
  49. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  50. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  51. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  52. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  53. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  54. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  55. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
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