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Method and apparatus for characterized parasitic capacitance between integrated-circuit interconnects 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G01R-027/26
출원번호 US-0931956 (1997-09-17)
발명자 / 주소
  • Nassif Sani Richard
출원인 / 주소
  • International Business Machines Corporation
대리인 / 주소
    Salys
인용정보 피인용 횟수 : 65  인용 특허 : 11

초록

A method and apparatus for characterizing dimensions and parasitic capacitance between integrated-circuit interconnects are disclosed. The apparatus is a test structure including at least two substantially identical oscillators, at least two substantially identical counters, and a pulse generator. E

대표청구항

[ What is claimed is:] [1.] A test structure for characterizing relative parasitic capacitances of a plurality of integrated-circuit interconnects, wherein said test structure is embedded within an integrated-circuit, said test structure comprising:at least one oscillator connected to a plurality of

이 특허에 인용된 특허 (11)

  1. Sanders Gary G. (Rock Falls IL) Goodwin Brian J. (Rock Falls IL), Apparatus and method for measuring capacitance from the duration of a charge-discharge charge cycle.
  2. Mills Frank S. (Minneapolis MN), Calibrated physical parameter value measurement system.
  3. Schaaf Robert L. (Vestal NY) Olsen Floyd W. (Athens PA) Tasillo Edward J. (Newark Valley NY), Capacitance and leakage test method and apparatus.
  4. Adams Charles K. (St. Louis MO), Capacitance detecting system and method for testing wire connections.
  5. Carusillo Steven J. (Elkhart IN), Capacitance transducing method and apparatus.
  6. Tielert Reinhard,DEX ; Hildebrandt Andreas,DEX, Circuit arrangement and method for measuring a difference in capacitance between a first capacitance C.sub.1 and a secon.
  7. Brihier Gerard C. C. (Ollainville FRX), Device for measuring the relative position of two objects.
  8. Doubek Edward R. (Naperville IL) Kasprzyk Marlon Z. (Westchester IL), Digital capacitance measuring test set and test circuit incorporated therein.
  9. Grace James R. (Cromwell CT), Method and apparatus for testing circuit boards.
  10. Caliboso Amado A. (Sunnyvale CA) Dabney ; Jr. S. Fred (Saratoga CA), Method and apparatus to measure capacitance.
  11. Boos Robert E. (Chandler AZ), Method for measuring capacitive loads.

이 특허를 인용한 특허 (65)

  1. Pitkethly, Scott; Masleid, Robert Paul, Advanced repeater utilizing signal distribution delay.
  2. Pitkethly, Scott, Advanced repeater with duty cycle adjustment.
  3. Pitkethly, Scott, Advanced repeater with duty cycle adjustment.
  4. Pitkethly, Scott, Advanced repeater with duty cycle adjustment.
  5. Corr, William E., Apparatus and method for determining effect of on-chip noise on signal propagation.
  6. Corr, William E., Apparatus and method for determining effect of on-chip noise on signal propagation.
  7. Corr, William E., Apparatus and method for determining effect of on-chip noise on signal propagation.
  8. Corr, William E., Apparatus and method for determining effect of on-chip noise on signal propagation.
  9. Corr, William E., Apparatus and method for determining effect of on-chip noise on signal propagation.
  10. Corr, William E., Apparatus and method for determining effect of on-chip noise on signal propagation.
  11. Corr, William E., Apparatus and method for determining effect of on-chip noise on signal propagation.
  12. Van Horn,Mark T.; Hedden,Richard N.; Cuthbert,David R.; Schoenfeld,Aaron M., Apparatus and methods for measuring parasitic capacitance and inductance of I/O leads on an electrical component using a network analyzer.
  13. Van Horn,Mark T.; Hedden,Richard N.; Cuthbert,David R.; Schoenfeld,Aaron M., Apparatus for measuring parasitic capacitance and inductance of I/O leads on an electrical component using a network analyzer.
  14. Van Horn,Mark T.; Hedden,Richard N.; Cuthbert,David R.; Schoenfeld,Aaron M., Apparatus for measuring parasitic capacitance and inductance of I/O leads on an electrical component using a network analyzer.
  15. Van Horn,Mark T.; Hedden,Richard N.; Cuthbert,David R.; Schoenfeld,Aaron M., Apparatus for measuring parasitic capacitance and inductance of I/O leads on an electrical component using a network analyzer.
  16. Van Horn,Mark T.; Hedden,Richard N.; Cuthbert,David R.; Schoenfeld,Aaron M., Apparatus for measuring parasitic capacitance and inductance of I/O leads on an electrical component using a network analyzer.
  17. Yuan, Xiao-Jie; Hart, Michael J.; Ling, Zicheng G.; Young, Steven P., Characterizing circuit performance by separating device and interconnect impact on signal delay.
  18. Yuan,Xiao Jie; Hart,Michael J.; Ling,Zicheng G.; Young,Steven P., Characterizing circuit performance by separating device and interconnect impact on signal delay.
  19. Yuan,Xiao Jie; Hart,Michael J.; Ling,Zicheng G.; Young,Steven P., Characterizing circuit performance by separating device and interconnect impact on signal delay.
  20. Masleid, Robert Paul; Dholabhai, Vatsal, Circuit with enhanced mode and normal mode.
  21. Masleid, Robert Paul; Kowalczyk, Andre, Circuits and methods for detecting and assisting wire transitions.
  22. Masleid, Robert, Circuits, systems and methods relating to a dynamic dual domino ring oscillator.
  23. Masleid,Robert P., Circuits, systems and methods relating to dynamic ring oscillators.
  24. Masleid, Robert Paul, Column select multiplexer circuit for a domino random access memory array.
  25. Masleid,Robert P., Column select multiplexer circuit for a domino random access memory array.
  26. Masleid, Robert Paul, Configurable delay chain with stacked inverter delay elements.
  27. Masleid, Robert Paul, Configurable delay chain with switching control for tail delay elements.
  28. Masleid, Robert Paul, Configurable tapered delay chain with multiple sizes of delay elements.
  29. Trimberger, Stephen M., Copy protection without non-volatile memory.
  30. Trimberger,Stephen M., Copy protection without non-volatile memory.
  31. Masleid, Robert P.; Pitkethly, Scott, Cross point switch.
  32. Masleid, Robert P.; Pitkethly, Scott, Cross point switch.
  33. Masleid, Robert P.; Pitkethly, Scott, Cross point switch.
  34. Masleid, Robert P, Dynamic ring oscillators.
  35. Trimberger, Stephen M., Intellectual property core protection for integrated circuits.
  36. Masleid, Robert P, Inverting zipper repeater circuit.
  37. Masleid, Robert P., Inverting zipper repeater circuit.
  38. Masleid, Robert Paul, Inverting zipper repeater circuit.
  39. Masleid, Robert, Leakage efficient anti-glitch filter.
  40. Smith Howard H. ; Deutsch Alina ; Tong Ching-Lung L. ; Nijhuis Rolf H., Method and system for characterizing coupling capacitance between integrated circuit interconnects.
  41. Van Horn,Mark T.; Hedden,Richard N.; Cuthbert,David R.; Schoenfeld,Aaron M., Methods for measuring parasitic capacitance and inductance of I/O leads on an electrical component using a network analyzer.
  42. Van Horn,Mark T.; Hedden,Richard N.; Cuthbert,David R.; Schoenfeld,Aaron M., Methods for measuring parasitic capacitance and inductance of I/O leads on an electrical component using a network analyzer.
  43. Novikov, Lenny M.; Anderson, Lenworth, Micropower voltage-independent capacitance measuring method and circuit.
  44. Arora,Narain D.; Pirogova,Rimma A., Non-contact method and apparatus for on-line interconnect characterization in VLSI circuits.
  45. Pavithran, Praveen; Pelgrom, Marcel; Wieling, Jean; Veendrick, Hendricus Joseph, On silicon interconnect capacitance extraction.
  46. Masleid, Robert Paul, Power efficient multiplexer.
  47. Masleid, Robert Paul, Power efficient multiplexer.
  48. Masleid, Robert Paul, Power efficient multiplexer.
  49. Masleid, Robert Paul, Power efficient multiplexer.
  50. Trimberger, Stephen M., Protecting a design for an integrated circuit using a unique identifier.
  51. Masleid, Robert Paul; Dholabhai, Vatsal; Klingner, Christian, Repeater circuit having different operating and reset voltage ranges, and methods thereof.
  52. Masleid, Robert Paul; Dholabhai, Vatsal, Repeater circuit with high performance repeater mode and normal repeater mode, wherein high performance repeater mode has fast reset capability.
  53. Masleid, Robert Paul; Sousa, Jose; Kottapalli, Venkata, Scannable dynamic circuit latch.
  54. Masleid, Robert P.; Burr, James B., Stacked inverter delay chain.
  55. Suzuki, Shingo, System and method for measuring negative bias thermal instability with a ring oscillator.
  56. Suzuki, Shingo, System and method for measuring negative bias thermal instability with a ring oscillator.
  57. Suzuki,Shingo, System and method for measuring negative bias thermal instability with a ring oscillator.
  58. Suzuki,Shingo, System and method for measuring negative bias thermal instability with a ring oscillator.
  59. Suzuki,Shingo, System and method for measuring negative bias thermal instability with a ring oscillator.
  60. Suzuki,Shingo, System and method for measuring time dependent dielectric breakdown with a ring oscillator.
  61. Pitkethly, Scott; Masleid, Robert P., Triple latch flip flop system and method.
  62. Pitkethly,Scott; Masleid,Robert P., Triple latch flip flop system and method.
  63. Trimberger, Stephen M.; Lesea, Austin H., Unique identifier derived from an intrinsic characteristic of an integrated circuit.
  64. Moore, Brian, Wireless radio frequency technique design and method for testing of integrated circuits and wafers.
  65. Moore,Brian, Wireless radio frequency technique design and method for testing of integrated circuits and wafers.
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