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Programmable delay circuit having calibratable delays

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H03K-005/13
출원번호 US-0877923 (1997-06-18)
발명자 / 주소
  • Arkin Brian J.
출원인 / 주소
  • Credence Systems Corporation
대리인 / 주소
    Smith-Hill and Bedell
인용정보 피인용 횟수 : 58  인용 특허 : 13

초록

A programmable delay circuit produces an OUTPUT signal following an INPUT signal with a delay selected by input delay selection data. The delay circuit includes a tapped delay line, a multiplexer, a delay adjustment stage and a programmable encoder. The delay line includes a set of N delay elements

대표청구항

[ What is claimed is:] [1.] A programmable delay circuit for producing a FIRST OUTPUT signal in delayed response to an INPUT signal, wherein said FIRST OUTPUT signal lags said INPUT signal with a circuit delay referenced by input delay selection data, the delay circuit comprising:encoding means for

이 특허에 인용된 특허 (13)

  1. Hjerpe James J. (San Diego CA) Russell J. Dennis (LaMesa CA) Young Rocky M. Y. (Escondido CA), All digital phase locked loop.
  2. Gutierrez ; Jr. Alberto (Fort Collins CO) Koerner Christopher (Longmont CO) Goto Masaharu (Hanno CO JPX) Barnes James O. (Fort Collins CO), CMOS pseudo-NMOS programmable capacitance time vernier and method of calibration.
  3. Osaki Akitoshi (Itami JPX) Yamada Akira (Itami JPX), Delay circuit and latch circuit for controlling setup time and hold time of pulse signals.
  4. Herlein Richard F. (San Jose CA) Davis Jeffrey A. (Santa Clara CA), Delay line control system for automatic test equipment.
  5. Guo Bin (Cupertino CA) Kubinec James J. (Reno NV), Digital serializer and time delay regulator.
  6. Chu David C. (Woodside CA), Double vernier time interval measurement using triggered phase-locked oscillators.
  7. Ketzler John H. A. (White Bear Lake MN), Electronic clock tuning system.
  8. Gutierrez ; Jr. Alberto (Fort Collins CO) Koerner Christopher (Longmont CO), Fine/coarse wired-or tapped delay line.
  9. Andresen Bernhard H. (Dallas TX) Casasanta Joseph A. (Allen TX) Keeney Stanley C. (Dallas TX) Martin Robert C. (Dallas TX) Satoh Yoshinori (Plano TX), High performance digital phase locked loop.
  10. Wichman Shannon A. (Dallas TX) Ko Uming (Plano TX), High resolution digital phase locked loop with automatic recovery logic.
  11. Goto Masaharu (Hannou JPX), Timing adjustment circuit.
  12. Masuda Noboru (Tokorozawa JPX) Yamamoto Kazumichi (Hachioji JPX) Nakajima Kazunori (Kokubunji JPX) Okabe Toshihiro (Hadano JPX) Yamagiwa Akira (Hadano JPX) Yamagishi Mikio (Ome JPX) Koide Kazuo (Irum, Variable delay circuit and clock signal supply unit using the same.
  13. DeLisle Francis A. (Wappingers Falls NY) Jacoutot Alfred M. (Winooski VT), Variable self-correcting digital delay circuit.

이 특허를 인용한 특허 (58)

  1. DeMaris, James E.; Eby, Michael D., Adjustable memory self-timing circuit.
  2. Pitkethly, Scott; Masleid, Robert Paul, Advanced repeater utilizing signal distribution delay.
  3. Pitkethly, Scott, Advanced repeater with duty cycle adjustment.
  4. Pitkethly, Scott, Advanced repeater with duty cycle adjustment.
  5. Pitkethly, Scott, Advanced repeater with duty cycle adjustment.
  6. Logue, John D.; Ching, Alvin Y.; Lu, Wei Guang, Automatic tap delay calibration for precise digital phase shift.
  7. Chapman D. James ; Currin Jeffrey D., Calibratable programmable phase shifter.
  8. Masleid, Robert Paul; Dholabhai, Vatsal, Circuit with enhanced mode and normal mode.
  9. Masleid, Robert, Circuits, systems and methods relating to a dynamic dual domino ring oscillator.
  10. Masleid,Robert P., Circuits, systems and methods relating to dynamic ring oscillators.
  11. Masleid, Robert Paul, Column select multiplexer circuit for a domino random access memory array.
  12. Masleid, Robert Paul, Configurable delay chain with stacked inverter delay elements.
  13. Masleid,Robert Paul, Configurable delay chain with stacked inverter delay elements.
  14. Masleid, Robert Paul, Configurable delay chain with switching control for tail delay elements.
  15. Masleid, Robert Paul, Configurable tapered delay chain with multiple sizes of delay elements.
  16. Yoshikawa, Atsushi; Hagihara, Yasuhiko, Delay adjustment circuit and a clock generating circuit using the same.
  17. Jong-Cheol Lee KR; Hak-Soo Yu KR, Delay circuit having variable slope control and threshold detect.
  18. Murakami, Daisuke, Delay circuit, delay controller, memory controller, and information terminal.
  19. Pastorello Douglas F. ; King Eric T., Delay correction system and method for a voltage channel in a sampled data measurement system.
  20. Hassoun, Joseph H.; Goetting, F. Erich; Logue, John D., Delay lock loop with clock phase shifter.
  21. Morrison,Shawn K.; Pang,Raymond C., Digital clock manager capacitive trim unit.
  22. Pang,Raymond C.; Wong,Jennifer, Digital clock manager having cascade voltage switch logic clock paths.
  23. Young, Steven P.; Logue, John D.; Percey, Andrew K.; Goetting, F. Erich; Ching, Alvin Y., Digital phase shifter.
  24. Cohen, Daniel S.; Meyer, Daniel J., Dual phase pulse modulation decoder circuit.
  25. Cohen,Daniel S.; Fagan,John L.; Bossard,Mark A., Dual phase pulse modulation encoder circuit.
  26. Masleid, Robert P, Dynamic ring oscillators.
  27. Pastorello, Douglas F.; King, Eric T., Energy-to-pulse converter systems, devices, and methods wherein the output frequency is greater than the calculation frequency and having output phasing.
  28. Chansungsan,Chaiyuth, Interpolator circuit.
  29. Masleid, Robert P, Inverting zipper repeater circuit.
  30. Masleid, Robert P., Inverting zipper repeater circuit.
  31. Masleid, Robert Paul, Inverting zipper repeater circuit.
  32. Masleid, Robert, Leakage efficient anti-glitch filter.
  33. Welker, James A.; Sanchez, Hector; Siegel, Joshua, Memory controller calibration.
  34. LaBerge, Paul A., Method and apparatus for an adjustable delay circuit having arranged serially coarse stages received by a fine delay stage.
  35. Maksimovic,Dragan; Dhar,Sandeep, Method and system for providing self-calibration for adaptively adjusting a power supply voltage in a digital processing system.
  36. Cohen,Daniel S.; Meyer,Daniel J.; Fagan,John L., Method for performing dual phase pulse modulation.
  37. Cao, Lipeng; Mai, Khoi B.; Sanchez, Hector, Multiple-stage, signal edge alignment apparatus and methods.
  38. Percey,Andrew K.; Pang,Raymond C., Phase matched clock divider.
  39. Masleid, Robert Paul, Power efficient multiplexer.
  40. Masleid, Robert Paul, Power efficient multiplexer.
  41. Masleid, Robert Paul, Power efficient multiplexer.
  42. Masleid, Robert Paul, Power efficient multiplexer.
  43. Masleid,Robert Paul, Power efficient multiplexer.
  44. Wang,Bonnie I; Huang,Joseph; Sung,Chiakang; Wang,Xiaobao; Kim,In Whan; Yeung,Wayne; Nguyen,Khai, Programmable phase shift circuitry.
  45. Atyunin,Vasily Grigorievich; Deas,Alexander Roger, Programmable self-calibrating vernier and method.
  46. Henzler, Stephan; Schimper, Markus; Madoglio, Paolo; Pellerano, Stefano; Chandrashekar, Kailash, Redundant delay digital-to-time converter.
  47. Masleid, Robert Paul; Dholabhai, Vatsal; Klingner, Christian, Repeater circuit having different operating and reset voltage ranges, and methods thereof.
  48. Masleid, Robert Paul; Dholabhai, Vatsal, Repeater circuit with high performance repeater mode and normal repeater mode, wherein high performance repeater mode has fast reset capability.
  49. Stoiber, Steven T.; Siu, Stuart, Ring based impedance control of an output driver.
  50. Stoiber, Steven T.; Siu, Stuart, Ring based impedance control of an output driver.
  51. Masleid, Robert P.; Burr, James B., Stacked inverter delay chain.
  52. Currin Jeffrey D. ; Herbold Jacob ; Reddy Manohari ; Dahl Mark ; Kuglin Philip T., System for linearizing a programmable delay circuit.
  53. Avants,Bradley S.; Yanez,Arturo, Systems and methods for implementing delay line circuitry.
  54. Foley, David P., Timing generator for generating high resolution pulses having arbitrary widths.
  55. Oh,Kwansuhk; Pang,Raymond C., Trim unit having less jitter.
  56. Atsumasa Sako JP, Variable delay circuit and semiconductor integrated circuit having the same.
  57. Yamaoka Nobusuke,JPX, Voltage-controlled delay line, direct phase controlled voltage-controlled oscillator, clock/data recovery circuit, and clock/data recovery apparatus.
  58. Cohen,Daniel S., Wide window decoder circuit for dual phase pulse modulation.
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