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Methods for depositing premetal dielectric layer at sub-atmospheric and high temperature conditions 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/44
출원번호 US-0748960 (1996-11-13)
발명자 / 주소
  • Xia Li-Qun
  • Yieh Ellie
  • Nemani Srinivas
출원인 / 주소
  • Applied Materials, Inc.
대리인 / 주소
    Townsend & Townsend & Crew
인용정보 피인용 횟수 : 72  인용 특허 : 8

초록

The present invention provides systems, methods and apparatus for high temperature (at least about 500-800.degree. C.) processing of semiconductor wafers. The systems, methods and apparatus of the present invention allow multiple process steps to be performed in situ in the same chamber to reduce to

대표청구항

[ What is claimed is:] [1.] A process for depositing an insulating layer on a substrate on a heater in a chamber, said process comprising the steps of:heating said heater to a temperature of at least about 500.degree. C. and below a reflow temperature of a phosphosilicate glass (PSG) film to be depo

이 특허에 인용된 특허 (8)

  1. Wang David N. (Cupertino CA) White John M. (Hayward CA) Law Kam S. (Union City CA) Leung Cissy (Union City CA) Umotoy Salvador P. (Pittsburg CA) Collins Kenneth S. (San Jose CA) Adamik John A. (San R, CVD of silicon oxide using TEOS decomposition and in-situ planarization process.
  2. Shibata Fumio (Kudamatsu JPX) Nagatomo Katsuaki (Kudamatsu JPX) Fukuhara Hidetomo (Kudamatsu JPX) Marumoto Gen (Kudamatsu JPX) Okudaira Sadayuki (Oume JPX), Method and apparatus for plasma process.
  3. Keller Christopher G. (Albany CA), Method for fabrication of high vertical aspect ratio thin film structures.
  4. Koh Chao-Ming (Hsinchu TWX) Liu Bin (Taipei TWX), Method for planarizing high step-height integrated circuit structures.
  5. Ema Taiji,JPX, Method of producing a fin-shaped capacitor.
  6. Ikemasu Shinichiro (Kawasaki JPX) Ema Taiji (Kawasaki JPX) Katayama Masaya (Kawasaki JPX), Method of producing a semiconductor device using a reticle having a polygonal shaped hole.
  7. Maydan Dan (Los Altos Hills CA) Somekh Sasson (Redwood City CA) Wang David N. (Cupertino CA) Cheng David (San Jose CA) Toshima Masato (San Jose CA) Harari Isaac (Mountain View CA) Hoppe Peter D. (Sun, Multi-chamber integrated process system.
  8. Karnett Martin P. (Catonsville MD), Tapered wet etching of contacts using a trilayer silox structure.

이 특허를 인용한 특허 (72)

  1. Kang, Sean; Ko, Jungmin; Luere, Oliver, Airgap formation with damage-free copper.
  2. Zhu,Wenxian; Yu,Jengyi; Sutanto,Siswanto; Sun,Pingsheng; Lowe,Jeffrey Chih Hou; Fung,Waikit; Poon,Tze Wing, Biased Hetch process in deposition-etch-deposition gap fill.
  3. Benjaminson, David; Lubomirsky, Dmitry; Math, Ananda Seelavanth; Natarajan, Saravanakumar; Chourey, Shubham, Bolted wafer chuck thermal management systems and methods for wafer processing systems.
  4. Shimbayashi, Koji, Capacitive element using MOS transistors.
  5. Lubomirsky, Dmitry, Chamber with flow-through source.
  6. Park, Hyung Sang; Choi, Seung Woo; Kim, Jong Su; Jung, Dong Rak; Lee, Jeong Ho; Lee, Chun Soo, Deposition apparatus.
  7. Park, Hyung Sang; Choi, Seung Woo; Kim, Jong Su; Jung, Dong Rak; Lee, Jeong Ho; Lee, Chun Soo, Deposition apparatus.
  8. Pan,Rong; Ton,Van Q., Deposition of thick BPSG layers as upper and lower cladding for optoelectronics applications.
  9. Papasouliotis,George D.; Goldner,Edith; Gauri,Vishal; Rahman,Md Sazzadur; Singh,Vikram, Deposition profile modification through process chemistry.
  10. Wesley Natzle ; Richard A. Conti ; Laertis Economikos ; Thomas Ivers ; George D. Papasouliotis, Directional CVD process with optimized etchback.
  11. Papasouliotis,George D.; Bayman,Atiye, Dynamic modification of gap fill process characteristics.
  12. Jin, Xiaoliang; Wang, Shulin; Luo, Lee; Ho, Henry; Chen, Steven A., Emissivity-change-free pumping plate kit in a single wafer chamber.
  13. Luo, Lee; Ho, Henry; Wang, Shulin; Tran, Binh Hoa; Tam, Alexander; Sanchez, Errol A. C.; Tao, Xianzhi; Chen, Steven A., Emissivity-change-free pumping plate kit in a single wafer chamber.
  14. Choi, Dongwon; Lee, Dong Hyung; Poon, Tze; Vellaikal, Manoj; Porshnev, Peter; Foad, Majeed, Enhanced scavenging of residual fluorine radicals using silicon coating on process chamber walls.
  15. Bayman,Atiye; Rahman,Md Sazzadur; Zhang,Weijie; van Schravendijk,Bart; Gauri,Vishal; Papasouliotis,George D.; Singh,Vikram, Gap fill for high aspect ratio structures.
  16. Korolik, Mikhail; Ingle, Nitin; Kioussis, Dimitri, Germanium etching systems and methods.
  17. Nguyen,Minh Anh; Lang,Chi I; Zhu,Wenxian; Huang,Judy H., Halogen-free noble gas assisted Hplasma etch process in deposition-etch-deposition gap fill.
  18. Lang,Chi I; Zhu,Wenxian; Limdulpaiboon,Ratsamee; Huang,Judy H., Helium-based etch process in deposition-etch-deposition gap fill.
  19. Shanker,Sunil; Cox,Sean; Lang,Chi I; Huang,Judy H.; Nguyen,Minh Anh; Vo,Ken; Zhu,Wenxian, Hydrogen treatment enhanced gap fill.
  20. Olmer, Leonard J.; Jones, Robert F.; Bevers, William D.; Martin, Jr., Edward P., In-situ removal of surface impurities prior to arsenic-doped polysilicon deposition in the fabrication of a heterojunction bipolar transistor.
  21. Starner, Alan L., Inertial temperature control system and method.
  22. Sutanto,Siswanto; Zhu,Wenxian; Fung,Waikit; Lim,Mayasari; Gauri,Vishal; Papasouliotis,George D., Method for controlling etch process repeatability.
  23. Lee, Ho Seok; Kim, Dong Sauk; Kim, Jin Woong, Method for forming contact hole of semiconductor device.
  24. Xia Li-qun ; Lim Tian-hoe ; Nguyen Huong Thanh ; Sugiarto Dian, Method for using bypass lines to stabilize gas flow and maintain plasma inside a deposition chamber.
  25. Papasouliotis, George D.; Tas, Robert D., Method of chemical modification of structure topography.
  26. Guenther, Rolf A.; Hammill, Curtis B., Method of fabricating a heated substrate support.
  27. Li, Zihui; Kao, Chia-Ling; Wang, Anchuan; Ingle, Nitin K., Methods for anisotropic control of selective silicon removal.
  28. Den Broeder Friedrich J. A.,NLX ; Hanzen Ralph M. N.,NLX ; Duine Peter A.,NLX ; Jungblut Reiner M.,NLX ; Draijer Cornelis,NLX ; Roozeboom Freddy,NLX ; Van Der Sluis Paul,NLX, Optical switching device.
  29. Lubomirsky, Dmitry, Oxygen compatible plasma source.
  30. Lee,Chun Soo; Oh,Min Sub; Park,Hyung Sang, Plasma enhanced atomic layer deposition (PEALD) equipment and method of forming a conducting thin film using the same thereof.
  31. Lubomirsky, Dmitry, Plasma processing system with direct outlet toroidal plasma source.
  32. Choi, Tom; Ko, Jungmin; Kang, Sean, Poly directional etch by oxidation.
  33. Bayman,Atiye; Papasouliotis,George D.; Ling,Yong; Zhang,Weijie; Gauri,Vishal; Lim,Mayasari, Process modulation to prevent structure erosion during gap fill.
  34. van Schravendijk, Bart; Hill, Richard S.; van den Hoek, Wilbert; te Nijenhuis, Harald, Protective layer to enable damage free gap fill.
  35. Hauf, Markus; Tay, Sing-Pin; Hu, Yao Zhi, Rapid thermal processing system for integrated circuits.
  36. Tay, Sing-Pin; Hu, Yao Zhi, Rapid thermal processing system for integrated circuits.
  37. Xu, Lin; Chen, Zhijun; Huang, Jiayin; Wang, Anchuan, Removal methods for high aspect ratio structures.
  38. Hung, Mong-Chi; Wu, Pin-Huan; Yang, Cheng-Lung, SABPSG process real temperature monitor.
  39. Wang, Xikun; Lei, Jianxin; Ingle, Nitin; Shaviv, Roey, Selective cobalt removal for bottom up gapfill.
  40. Wang, Xikun; Ingle, Nitin, Selective in situ cobalt residue removal.
  41. Wang, Xikun; Ingle, Nitin, Selective tungsten removal.
  42. Arnepalli, Ranga Rao; Goradia, Prerna Sonthalia; Visser, Robert Jan; Ingle, Nitin; Korolik, Mikhail; Biswas, Jayeeta; Lodha, Saurabh, Self-limiting atomic thermal etching systems and methods.
  43. Shimbayashi, Koji, Semiconductor device and method of manufacturing the same.
  44. Lubomirsky, Dmitry; Chen, Xinglong; Venkataraman, Shankar, Semiconductor processing systems having multiple plasma configurations.
  45. Yang, Jang-Gyoo; Chen, Xinglong; Park, Soonam; Baek, Jonghoon; Garg, Saurabh; Venkataraman, Shankar, Semiconductor processing with DC assisted RF power for improved control.
  46. Liaw Jhon-Jhy,TWX ; Lee Jin-Yuan,TWX ; Lee Kuei-Ying,TWX ; Fu Chu-Yun,TWX ; Thei Kong-Beng,TWX, Shallow trench isolation methods employing gap filling doped silicon oxide dielectric layer.
  47. Ko, Jungmin; Choi, Tom; Ingle, Nitin; Kim, Kwang-Soo; Wou, Theodore, SiN spacer profile patterning.
  48. Li-Qun Xia ; Paul Fisher ; Margaret Lynn Gotuaco ; Frederic Gaillard FR; Ellie Yieh, Silicon carbide cap layers for low dielectric constant silicon oxide layers.
  49. Huang, Jiayin; Chen, Zhijun; Wang, Anchuan; Ingle, Nitin, Silicon pretreatment for nitride removal.
  50. Lang,Chi i; Limdulpaiboon,Ratsamee; Gonzalez,Cayetano, Strain engineering--HDP thin film with tensile stress for FEOL and other applications.
  51. Yu,Jengyi; Lang,Chi I; Huang,Judy H., Stress profile modulation in STI gap fill.
  52. Nakano, Minoru; Ueno, Masaaki, Temperature control method and semiconductor device manufacturing method.
  53. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
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