초록 ▼

The capacity of a cache memory is substantially reduced over that required for a multi-chip distributed shared memory (DSM) implementation to enable the cache memory, a main memory, a processor and requisite logic and control circuitry to fit on a single integrated circuit chip. The increased cache

The capacity of a cache memory is substantially reduced over that required for a multi-chip distributed shared memory (DSM) implementation to enable the cache memory, a main memory, a processor and requisite logic and control circuitry to fit on a single integrated circuit chip. The increased cache miss rate created by the reduced cache memory capacity is compensated for by the reduced cache miss resolution period resulting from integrating the main memory and processor on the single chip. The reduced cache miss resolution period enables the processor clock rate to be substantially increased, so that a processor having a simple functionality such as a reduced instruction set computer (RISC) processor can be utilized and still provide the required processing speed. The RISC processor is substantially smaller than a more complicated processor that would be required to provide the same processing speed in a multi-chip DSM implementation, thereby enabling the RISC processor to fit on the chip with the other elements. A single-chip communications node that can be used in telecommunications networks other than DSM includes a memory controller for providing local and remote memory coherency, and a bidirectional interconnect unit that converts memory access instructions into memory access messages and vice-versa.

대표청구항 ▼

[ We claim:] [1.] A single integrated circuit chip distributed shared memory (DSM) node that is capable of operating at a predetermined processing speed, comprising:a computing unit integral with said chip, comprising a processor, a cache controller, and a cache memory;a main memory integral with sa

[ We claim:] [1.] A single integrated circuit chip distributed shared memory (DSM) node that is capable of operating at a predetermined processing speed, comprising:a computing unit integral with said chip, comprising a processor, a cache controller, and a cache memory;a main memory integral with said chip;a bidirectional interconnect unit integral with said chip for connection to a remote node; anda memory controller integral with said chip for interconnecting the processor, cache controller, cache memory, main memory and bidirectional interconnect unit and maintaining memory coherency between the cache memory, main memory and said remote node, wherein said memory controller includes a directory controller that stores and modifies a directory in the main memory; in whichthe cache memory has a capacity that is sufficiently small to enable the cache memory to fit on said chip but creates a substantial cache miss rate; andthe main memory has a cache miss resolution period that is sufficiently small to compensate for said cache miss rate and enable the node to operate at said predetermined processing speed.