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Nonvolatile memory array with NAND string memory cell groups selectively connected to sub bit lines 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G11C-016/06
출원번호 US-0015787 (1998-01-29)
우선권정보 JP-0018566 (1997-01-31)
발명자 / 주소
  • Arase Kenshiro,JPX
출원인 / 주소
  • Sony Corporation, JPX
대리인 / 주소
    Kananen
인용정보 피인용 횟수 : 62  인용 특허 : 4

초록

A semiconductor nonvolatile memory device where a main bit line is divided into a plurality of sub bit lines via operational connecting means, memory transistors connected to the sub bit lines are arranged in the form of a matrix, and control gate electrodes of these memory transistors are connected

대표청구항

[ What is claimed is:] [1.] A semiconductor nonvolatile memory device, comprising:a plurality of main bit lines each divided into a plurality of sub bit lines via selective connecting means,a plurality of word lines,a plurality of memory transistors connected to the sub bit lines and arranged in a m

이 특허에 인용된 특허 (4)

  1. Hu Chung-You, Bias scheme of program inhibit for random programming in a nand flash memory.
  2. Iwahashi Hiroshi,JPX, Electrically programmable nonvolatile semiconductor memory device with NAND cell structure.
  3. Nobukata Hiromi (Kanagawa JPX) Satori Kenichi (Kanagawa JPX), Nonvolatile memory device with NAND array.
  4. Juergens Eugene H. (Grafton WI) Novesky Timothy A. (Grafton WI) Rychtik Jerome (Grafton WI), Tractor trailer integrated jackknife control device.

이 특허를 인용한 특허 (62)

  1. Lee, Hee Youl, 3D multi-layer non-volatile memory device with planar string and method of programming.
  2. Goda, Akira; Ahmed, Shafqat; Hasnat, Khaled; Parat, Krishna K., Apparatus and methods including source gates.
  3. Goda, Akira; Ahmed, Shafqat; Hasnat, Khaled; Parat, Krishna K., Apparatus and methods including source gates.
  4. Goda, Akira; Ahmed, Shafqat; Hasnat, Khaled; Parat, Krishna K., Apparatus and methods including source gates.
  5. Li,Yan; Pham,Long, Apparatus for programming of multi-state non-volatile memory using smart verify.
  6. Chen, Jian; Lutze, Jeffrey W.; Li, Yan; Guterman, Daniel C.; Tanaka, Tomoharu, Behavior based programming of non-volatile memory.
  7. Chen,Jian; Lutze,Jeffrey W.; Li,Yan; Guterman,Daniel C.; Tanaka,Tomoharu, Behavior based programming of non-volatile memory.
  8. Lee,Shih Chung, Coarse/fine program verification in non-volatile memory using different reference levels for improved sensing.
  9. Kim, Jongoh; Kwon, Yi-Jin; Liu, Cheng-Jye, Decoding method in an NROM flash memory array.
  10. Winograd, Gil I.; Afghahi, Morteza Cyrus; Terzioglu, Esin, Dense read-only memory.
  11. Duzly, Yacov; Marcu, Alon; Kenan, Yuval; Li, Yan; Mui, Man Lung; Lee, Seungpil, Fast-reading NAND flash memory.
  12. Duzly, Yacov; Marcu, Alon; Kenan, Yuval; Li, Yan; Mui, Man; Lee, Seungpil, Fast-reading NAND flash memory.
  13. Lee, Jin-Wook; Hwang, Sang-Won, Flash memory device with split string selection line structure.
  14. Kim, Jin-Ki, Flash memory program inhibit scheme.
  15. Kim, Jin-Ki, Flash memory program inhibit scheme.
  16. Kim, Jin-Ki, Flash memory program inhibit scheme.
  17. Kim,Jin Ki, Flash memory program inhibit scheme.
  18. Fasoli,Luca G.; Scheuerlein,Roy E., Integrated circuit including memory array incorporating multiple types of NAND string structures.
  19. Fasoli,Luca G.; Scheuerlein,Roy E.; Chen,En Hsing; Nallamothu,Sucheta; Mahajani,Maitreyee; Walker,Andrew J., Memory array incorporating mirrored NAND strings and non-shared global bit lines within a block.
  20. Sukegawa, Hiroshi; Nakano, Takeshi, Memory controller.
  21. Sukegawa, Hiroshi; Nakano, Takeshi, Memory controller.
  22. Muraoka, Shunsaku; Osano, Koichi; Takahashi, Ken; Shimotashiro, Masafumi, Memory device, memory circuit and semiconductor integrated circuit having variable resistance.
  23. Muraoka,Shunsaku; Osano,Koichi; Takahashi,Ken; Shimotashiro,Masafumi, Memory device, memory circuit and semiconductor integrated circuit having variable resistance.
  24. Li,Yan; Pham,Long, Method for programming of multi-state non-volatile memory using smart verify.
  25. Li,Yan; Pham,Long, Method for programming of multi-state non-volatile memory using smart verify.
  26. Kamei, Teruhiko; Li, Yan, Method for programming with initial programming voltage based on trial.
  27. Meyer, Steffen, Method of forming an integrated circuit with NAND flash array segments and intra array multiplexers and corresponding integrated circuit with NAND flash array segments and intra array multiplexers.
  28. Kwak, Donghun, Method of programming a 3-dimensional nonvolatile memory device based on a program order of a selected page and a location of a string selection line.
  29. Lee,Hee Youl, NAND flash memory device and method of reading the same.
  30. Chen,En Hsing; Walker,Andrew J.; Scheuerlein,Roy E.; Nallamothu,Sucheta; Ilkbahar,Alper; Fasoli,Luca G., NAND memory array incorporating capacitance boosting of channel regions in unselected memory cells and method for operation of same.
  31. Chen,En Hsing; Walker,Andrew J.; Scheuerlein,Roy E.; Nallamothu,Sucheta; Ilkbahar,Alper; Fasoli,Luca G., NAND memory array incorporating capacitance boosting of channel regions in unselected memory cells and method for operation of same.
  32. Matsunaga, Yasuhiko; Yaegashi, Toshitake; Arai, Fumitaka, NAND type flash EEPROM in which sequential programming process is performed by using different intermediate voltages.
  33. Matsunaga, Yasuhiko; Yaegashi, Toshitake; Arai, Fumitaka, NAND type flash EEPROM in which sequential programming process is performed by using different intermediate voltages.
  34. Toriyama, Shuichi; Matsuzawa, Kazuya, NAND type nonvolatile semiconductor memory device having sideface electrode shared by memory cells.
  35. Li, Yan; Lee, Seungpil; Chan, Siu Lung, Non-volatile memory and method with power-saving read and program-verify operations.
  36. Li, Yan; Lee, Seungpil; Chan, Siu Lung, Non-volatile memory and method with power-saving read and program-verify operations.
  37. Li, Yan; Lee, Seungpil; Chan, Siu Lung, Non-volatile memory and method with power-saving read and program-verify operations.
  38. Li,Yan; Lee,Seungpil; Chan,Siu Lung, Non-volatile memory and method with power-saving read and program-verify operations.
  39. Park,Jung Hoon, Non-volatile memory devices and methods of programming the same.
  40. Yoon, Young-bae; Choe, Jeong-dong; Kang, Hee-soo; Jang, Dong-hoon; Kim, Ki-hyun, Non-volatile memory devices including shared bit lines and methods of fabricating the same.
  41. Furuyama, Takaaki, Non-volatile semiconductor memory.
  42. Yano, Masaru, Non-volatile semiconductor memory device.
  43. Jeong, Jae-Yong; Lee, Sung-Soo, Non-volatile semiconductor memory device capable of preventing program disturb due to noise voltage induced at a string select line and program method thereof.
  44. Kamei, Teruhiko; Li, Yan, Non-volatile storage system with initial programming voltage based on trial.
  45. Kamei, Teruhiko; Li, Yan, Non-volatile storage system with initial programming voltage based on trial.
  46. Youn, Tae-Un, Nonvolatile memory device and reading method thereof.
  47. Abraham, Michael; Tanaka, Tomoharu; Kawai, Koichi; Einaga, Yuichi, Partial page memory operations.
  48. Scheuerlein,Roy E.; Petti,Christopher; Walker,Andrew J.; Chen,En Hsing; Nallamothu,Sucheta; Ilkbahar,Alper; Fasoli,Luca; Koutnetsov,Igor, Programmable memory array structure incorporating series-connected transistor strings and methods for fabrication and operation of same.
  49. Hwang, Soon Wook; Park, Ki Tae; Lee, Yeong Taek, Semiconductor memory device.
  50. Takahashi, Takeo, Semiconductor memory device.
  51. Takahashi, Takeo, Semiconductor memory device.
  52. Makoto Kojima JP, Semiconductor memory device having a hierarchical bit line architecture.
  53. Lee, Seung-Jae; Lim, Young-Ho, Semiconductor memory device having memory cell arrays capable of accomplishing random access.
  54. Shibata, Noboru, Semiconductor memory device including a NAND string.
  55. Tamada, Satoru, System and devices including memory resistant to program disturb and methods of using, making, and operating the same.
  56. Juengling, Werner, Systems and devices including local data lines and methods of using, making, and operating the same.
  57. Lee, Shih Chung, Systems for coarse/fine program verification in non-volatile memory using different reference levels for improved sensing.
  58. Scheuerlein, Roy E.; Ilkbahar, Alper; Fasoli, Luca G., Three-dimensional memory device incorporating segmented array line memory array.
  59. Scheuerlein, Roy E.; Ilkbahar, Alper; Fasoli, Luca G., Three-dimensional memory device incorporating segmented array line memory array.
  60. Scheuerlein,Roy E.; Ilkbahar,Alper; Fasoli,Luca, Three-dimensional memory device incorporating segmented bit line memory array.
  61. Scheuerlein,Roy E., Word line arrangement having multi-layer word line segments for three-dimensional memory array.
  62. Scheuerlein,Roy E., Word line arrangement having multi-layer word line segments for three-dimensional memory array.
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